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| author | Edgar E. Iglesias <edgar.iglesias@amd.com> | 2022-04-06 18:43:03 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-04-21 11:37:03 +0100 |
| commit | d6ccfc7e6734383926fccfdb92df238761cb9423 (patch) | |
| tree | ca2840af704d255c17fcabd39bda0791704a826c /.travis.yml | |
| parent | 369e5cb0c948b65e0845ca3394e25d757dd93206 (diff) | |
hw/arm: versal: Connect the CRL
Connect the CRL (Clock Reset LPD) to the Versal SoC.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Frederic Konrad <fkonrad@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20220406174303.2022038-5-edgar.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to '.travis.yml')
0 files changed, 0 insertions, 0 deletions