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authorMichael Clark <mjc@sifive.com>2019-01-14 23:58:23 +0000
committerPalmer Dabbelt <palmer@sifive.com>2019-02-11 15:56:21 -0800
commitfb73883964099011d34c052658e5ad8be049da61 (patch)
tree86f282b08a834767090233fdd02cc245b70e4561 /.travis.yml
parent7f2b5ff125d518a7fff9f6a4c633e3063fd75ec3 (diff)
RISC-V: Use riscv prefix consistently on cpu helpers
* Add riscv prefix to raise_exception function * Add riscv prefix to CSR read/write functions * Add riscv prefix to signal handler function * Add riscv prefix to get fflags function * Remove redundant declaration of riscv_cpu_init and rename cpu_riscv_init to riscv_cpu_init * rename riscv_set_mode to riscv_cpu_set_mode Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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