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authorRichard Henderson <richard.henderson@linaro.org>2021-09-17 11:08:09 -0700
committerRichard Henderson <richard.henderson@linaro.org>2021-10-30 09:52:04 -0700
commitba0e73336200a04f797ae0c13922146a135cb118 (patch)
tree09a3dd7150c4746ba5af15dc173e627d81de4d90 /.gitpublish
parent940b30904e928854250988c3802f334c8ee12bd4 (diff)
configure: Merge riscv32 and riscv64 host architectures
The existing code for safe-syscall.inc.S will compile without change for riscv32 and riscv64. We may also drop the meson.build stanza that merges them for tcg/. Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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