diff options
| author | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2023-03-02 13:37:04 +0000 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2023-03-07 12:39:00 -0500 |
| commit | 47f0e7ab3272737c174ca68c03843e0d1996dc22 (patch) | |
| tree | 288cb05131c3a7d69d3bbec3e295bda0cedd2292 /.gdbinit | |
| parent | 9a6ef182c03eaa138bae553f0fbb5a123bef9a53 (diff) | |
hw/pci-bridge/cxl_root_port: Wire up AER
We are missing necessary config write handling for AER emulation in
the CXL root port. Add it based on pcie_root_port.c
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Message-Id: <20230302133709.30373-4-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Diffstat (limited to '.gdbinit')
0 files changed, 0 insertions, 0 deletions