blob: 8f2e67db5ab733969e80c109932f7d5ea5533fce (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
|
/*
* ASPEED Interrupt Controller (New)
*
* Andrew Jeffery <andrew@aj.id.au>
*
* Copyright 2016 IBM Corp.
*
* This code is licensed under the GPL version 2 or later. See
* the COPYING file in the top-level directory.
*
* Need to add SVIC and CVIC support
*/
#ifndef ASPEED_VIC_H
#define ASPEED_VIC_H
#include "hw/sysbus.h"
#include "qom/object.h"
#define TYPE_ASPEED_VIC "aspeed.vic"
typedef struct AspeedVICState AspeedVICState;
DECLARE_INSTANCE_CHECKER(AspeedVICState, ASPEED_VIC,
TYPE_ASPEED_VIC)
#define ASPEED_VIC_NR_IRQS 51
struct AspeedVICState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
qemu_irq irq;
qemu_irq fiq;
uint64_t level;
uint64_t raw;
uint64_t select;
uint64_t enable;
uint64_t trigger;
/* 0=edge, 1=level */
uint64_t sense;
/* 0=single-edge, 1=dual-edge */
uint64_t dual_edge;
/* 0=low-sensitive/falling-edge, 1=high-sensitive/rising-edge */
uint64_t event;
};
#endif /* ASPEED_VIC_H */
|
