Unsolved issues/bugs in the mips/mipsel backend
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General
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- Unimplemented ASEs:
  - MIPS16
  - MDMX
  - SmartMIPS
  - DSP r1
  - DSP r2
- MT ASE only partially implemented and not functional
- Shadow register support only partially implemented,
  lacks set switching on interrupt/exception.
- 34K ITC not implemented.
- A general lack of documentation, especially for technical internals.
  Existing documentation is x86-centric.
- Reverse endianness bit not implemented
- The TLB emulation is very inefficient:
  Qemu's softmmu implements a x86-style MMU, with separate entries
  for read/write/execute, a TLB index which is just a modulo of the
  virtual address, and a set of TLBs for each user/kernel/supervisor
  MMU mode.
  MIPS has a single entry for read/write/execute and only one MMU mode.
  But it is fully associative with randomized entry indices, and uses
  up to 256 ASID tags as additional matching criterion (which roughly
  equates to 256 MMU modes). It also has a global flag which causes
  entries to match regardless of ASID.
  To cope with these differences, Qemu currently flushes the TLB at
  each ASID change. Using the MMU modes to implement ASIDs hinges on
  implementing the global bit efficiently.
- save/restore of the CPU state is not implemented (see machine.c).
- Improve cpu state handling:
  Step 1) Collect all the TC state in a single struct, so we need only
          a single global pointer per TC.
  Step 2) Use only a single TC context as working context, and copy the
          contexts on TC switch. Likewise for FPU contexts.

MIPS64
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- Userland emulation (both n32 and n64) not functional.

"Generic" 4Kc system emulation
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- Doesn't correspond to any real hardware.

PICA 61 system emulation
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- No framebuffer support yet.

MALTA system emulation
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- We fake firmware support instead of doing the real thing
- Real firmware falls over when trying to init RAM, presumably due
  to lacking system controller emulation.
- Bonito system controller not implemented
- MSC1 system controller not implemented