From 7848023ae43cf775fb211cc66bb2e17376ee23d3 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Thu, 28 Jan 2021 12:00:10 +0000 Subject: arm: rename xlnx-zcu102.canbusN properties The properties to attach a CANBUS object to the xlnx-zcu102 machine have a period in them. We want to use periods in properties for compound QAPI types, and besides the "xlnx-zcu102." prefix is both unnecessary and different from any other machine property name. Remove it. Signed-off-by: Paolo Bonzini Message-id: 20210118162537.779542-1-pbonzini@redhat.com Reviewed-by: Vikram Garhwal Signed-off-by: Peter Maydell --- tests/qtest/xlnx-can-test.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) (limited to 'tests') diff --git a/tests/qtest/xlnx-can-test.c b/tests/qtest/xlnx-can-test.c index 3d1120005b..54de71a686 100644 --- a/tests/qtest/xlnx-can-test.c +++ b/tests/qtest/xlnx-can-test.c @@ -138,9 +138,9 @@ static void test_can_bus(void) uint8_t can_timestamp = 1; QTestState *qts = qtest_init("-machine xlnx-zcu102" - " -object can-bus,id=canbus0" - " -machine xlnx-zcu102.canbus0=canbus0" - " -machine xlnx-zcu102.canbus1=canbus0" + " -object can-bus,id=canbus" + " -machine canbus0=canbus" + " -machine canbus1=canbus" ); /* Configure the CAN0 and CAN1. */ @@ -175,9 +175,9 @@ static void test_can_loopback(void) uint32_t status = 0; QTestState *qts = qtest_init("-machine xlnx-zcu102" - " -object can-bus,id=canbus0" - " -machine xlnx-zcu102.canbus0=canbus0" - " -machine xlnx-zcu102.canbus1=canbus0" + " -object can-bus,id=canbus" + " -machine canbus0=canbus" + " -machine canbus1=canbus" ); /* Configure the CAN0 in loopback mode. */ @@ -223,9 +223,9 @@ static void test_can_filter(void) uint8_t can_timestamp = 1; QTestState *qts = qtest_init("-machine xlnx-zcu102" - " -object can-bus,id=canbus0" - " -machine xlnx-zcu102.canbus0=canbus0" - " -machine xlnx-zcu102.canbus1=canbus0" + " -object can-bus,id=canbus" + " -machine canbus0=canbus" + " -machine canbus1=canbus" ); /* Configure the CAN0 and CAN1. */ @@ -271,9 +271,9 @@ static void test_can_sleepmode(void) uint8_t can_timestamp = 1; QTestState *qts = qtest_init("-machine xlnx-zcu102" - " -object can-bus,id=canbus0" - " -machine xlnx-zcu102.canbus0=canbus0" - " -machine xlnx-zcu102.canbus1=canbus0" + " -object can-bus,id=canbus" + " -machine canbus0=canbus" + " -machine canbus1=canbus" ); /* Configure the CAN0. */ @@ -317,9 +317,9 @@ static void test_can_snoopmode(void) uint8_t can_timestamp = 1; QTestState *qts = qtest_init("-machine xlnx-zcu102" - " -object can-bus,id=canbus0" - " -machine xlnx-zcu102.canbus0=canbus0" - " -machine xlnx-zcu102.canbus1=canbus0" + " -object can-bus,id=canbus" + " -machine canbus0=canbus" + " -machine canbus1=canbus" ); /* Configure the CAN0. */ -- cgit v1.2.3 From 1e5ce6e10a1deaec6044ba8ad75431e0424dbce9 Mon Sep 17 00:00:00 2001 From: Hao Wu Date: Tue, 26 Jan 2021 17:11:42 -0800 Subject: hw/misc: Fix arith overflow in NPCM7XX PWM module Fix potential overflow problem when calculating pwm_duty. 1. Ensure p->cmr and p->cnr to be from [0,65535], according to the hardware specification. 2. Changed duty to uint32_t. However, since MAX_DUTY * (p->cmr+1) can excceed UINT32_MAX, we convert them to uint64_t in computation and converted them back to uint32_t. (duty is guaranteed to be <= MAX_DUTY so it won't overflow.) Fixes: CID 1442342 Suggested-by: Peter Maydell Reviewed-by: Doug Evans Signed-off-by: Hao Wu Message-id: 20210127011142.2122790-1-wuhaotsh@google.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- tests/qtest/npcm7xx_pwm-test.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/qtest/npcm7xx_pwm-test.c b/tests/qtest/npcm7xx_pwm-test.c index 63557d2c06..3d82654b81 100644 --- a/tests/qtest/npcm7xx_pwm-test.c +++ b/tests/qtest/npcm7xx_pwm-test.c @@ -272,7 +272,7 @@ static uint64_t pwm_compute_freq(QTestState *qts, uint32_t ppr, uint32_t csr, static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted) { - uint64_t duty; + uint32_t duty; if (cnr == 0) { /* PWM is stopped. */ @@ -280,7 +280,7 @@ static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted) } else if (cmr >= cnr) { duty = MAX_DUTY; } else { - duty = MAX_DUTY * (cmr + 1) / (cnr + 1); + duty = (uint64_t)MAX_DUTY * (cmr + 1) / (cnr + 1); } if (inverted) { -- cgit v1.2.3 From 677726ef1ebc567e4f5081f68623debc68f958d9 Mon Sep 17 00:00:00 2001 From: Mihai Carabas Date: Wed, 27 Jan 2021 16:59:27 +0200 Subject: hw/misc/pvpanic: split-out generic and bus dependent code To ease the PCI device addition in next patches, split the code as follows: - generic code (read/write/setup) is being kept in pvpanic.c - ISA dependent code moved to pvpanic-isa.c Also, rename: - ISA_PVPANIC_DEVICE -> PVPANIC_ISA_DEVICE. - TYPE_PVPANIC -> TYPE_PVPANIC_ISA. - MemoryRegion io -> mr. - pvpanic_ioport_* in pvpanic_*. Update the build system with the new files and config structure. Signed-off-by: Mihai Carabas Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- tests/qtest/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 16d04625b8..0e85343b96 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -33,7 +33,7 @@ qtests_i386 = \ (config_host.has_key('CONFIG_LINUX') and \ config_all_devices.has_key('CONFIG_ISA_IPMI_BT') ? ['ipmi-bt-test'] : []) + \ (config_all_devices.has_key('CONFIG_WDT_IB700') ? ['wdt_ib700-test'] : []) + \ - (config_all_devices.has_key('CONFIG_PVPANIC') ? ['pvpanic-test'] : []) + \ + (config_all_devices.has_key('CONFIG_PVPANIC_ISA') ? ['pvpanic-test'] : []) + \ (config_all_devices.has_key('CONFIG_HDA') ? ['intel-hda-test'] : []) + \ (config_all_devices.has_key('CONFIG_I82801B11') ? ['i82801b11-test'] : []) + \ (config_all_devices.has_key('CONFIG_IOH3420') ? ['ioh3420-test'] : []) + \ -- cgit v1.2.3 From c0f82826a1cc52a2a038b12ccaa1c92bb7e2d4c0 Mon Sep 17 00:00:00 2001 From: Mihai Carabas Date: Wed, 27 Jan 2021 16:59:30 +0200 Subject: tests/qtest: add a test case for pvpanic-pci Add a test case for pvpanic-pci device. The scenario is the same as pvpanic ISA device, but is using the PCI bus. Signed-off-by: Mihai Carabas Acked-by: Thomas Huth Reviewed-by: Peter Maydell Signed-off-by: Mihai Carabas [PMM: added code to free dev and pcibus, which the oss-fuzz build otherwise complains about as a leak] Signed-off-by: Peter Maydell --- tests/qtest/meson.build | 1 + tests/qtest/pvpanic-pci-test.c | 98 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 99 insertions(+) create mode 100644 tests/qtest/pvpanic-pci-test.c (limited to 'tests') diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 0e85343b96..7ccdf02311 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -34,6 +34,7 @@ qtests_i386 = \ config_all_devices.has_key('CONFIG_ISA_IPMI_BT') ? ['ipmi-bt-test'] : []) + \ (config_all_devices.has_key('CONFIG_WDT_IB700') ? ['wdt_ib700-test'] : []) + \ (config_all_devices.has_key('CONFIG_PVPANIC_ISA') ? ['pvpanic-test'] : []) + \ + (config_all_devices.has_key('CONFIG_PVPANIC_PCI') ? ['pvpanic-pci-test'] : []) + \ (config_all_devices.has_key('CONFIG_HDA') ? ['intel-hda-test'] : []) + \ (config_all_devices.has_key('CONFIG_I82801B11') ? ['i82801b11-test'] : []) + \ (config_all_devices.has_key('CONFIG_IOH3420') ? ['ioh3420-test'] : []) + \ diff --git a/tests/qtest/pvpanic-pci-test.c b/tests/qtest/pvpanic-pci-test.c new file mode 100644 index 0000000000..2358852d35 --- /dev/null +++ b/tests/qtest/pvpanic-pci-test.c @@ -0,0 +1,98 @@ +/* + * QTest testcase for PV Panic PCI device + * + * Copyright (C) 2020 Oracle + * + * Authors: + * Mihai Carabas + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "libqos/libqtest.h" +#include "qapi/qmp/qdict.h" +#include "libqos/pci.h" +#include "libqos/pci-pc.h" +#include "hw/pci/pci_regs.h" + +static void test_panic_nopause(void) +{ + uint8_t val; + QDict *response, *data; + QTestState *qts; + QPCIBus *pcibus; + QPCIDevice *dev; + QPCIBar bar; + + qts = qtest_init("-device pvpanic-pci,addr=04.0 -action panic=none"); + pcibus = qpci_new_pc(qts, NULL); + dev = qpci_device_find(pcibus, QPCI_DEVFN(0x4, 0x0)); + qpci_device_enable(dev); + bar = qpci_iomap(dev, 0, NULL); + + qpci_memread(dev, bar, 0, &val, sizeof(val)); + g_assert_cmpuint(val, ==, 3); + + val = 1; + qpci_memwrite(dev, bar, 0, &val, sizeof(val)); + + response = qtest_qmp_eventwait_ref(qts, "GUEST_PANICKED"); + g_assert(qdict_haskey(response, "data")); + data = qdict_get_qdict(response, "data"); + g_assert(qdict_haskey(data, "action")); + g_assert_cmpstr(qdict_get_str(data, "action"), ==, "run"); + qobject_unref(response); + + g_free(dev); + qpci_free_pc(pcibus); + qtest_quit(qts); +} + +static void test_panic(void) +{ + uint8_t val; + QDict *response, *data; + QTestState *qts; + QPCIBus *pcibus; + QPCIDevice *dev; + QPCIBar bar; + + qts = qtest_init("-device pvpanic-pci,addr=04.0 -action panic=pause"); + pcibus = qpci_new_pc(qts, NULL); + dev = qpci_device_find(pcibus, QPCI_DEVFN(0x4, 0x0)); + qpci_device_enable(dev); + bar = qpci_iomap(dev, 0, NULL); + + qpci_memread(dev, bar, 0, &val, sizeof(val)); + g_assert_cmpuint(val, ==, 3); + + val = 1; + qpci_memwrite(dev, bar, 0, &val, sizeof(val)); + + response = qtest_qmp_eventwait_ref(qts, "GUEST_PANICKED"); + g_assert(qdict_haskey(response, "data")); + data = qdict_get_qdict(response, "data"); + g_assert(qdict_haskey(data, "action")); + g_assert_cmpstr(qdict_get_str(data, "action"), ==, "pause"); + qobject_unref(response); + + g_free(dev); + qpci_free_pc(pcibus); + qtest_quit(qts); +} + +int main(int argc, char **argv) +{ + int ret; + + g_test_init(&argc, &argv, NULL); + qtest_add_func("/pvpanic-pci/panic", test_panic); + qtest_add_func("/pvpanic-pci/panic-nopause", test_panic_nopause); + + ret = g_test_run(); + + return ret; +} -- cgit v1.2.3 From 30858dafd1edc0be613d0d6d1381d3fb94ef0747 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 28 Jan 2021 11:41:23 +0000 Subject: tests: Add a simple test of the CMSDK APB timer MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a simple test of the CMSDK APB timer, since we're about to do some refactoring of how it is clocked. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel Tested-by: Philippe Mathieu-Daudé Message-id: 20210128114145.20536-4-peter.maydell@linaro.org Message-id: 20210121190622.22000-4-peter.maydell@linaro.org --- tests/qtest/cmsdk-apb-timer-test.c | 75 ++++++++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 1 + 2 files changed, 76 insertions(+) create mode 100644 tests/qtest/cmsdk-apb-timer-test.c (limited to 'tests') diff --git a/tests/qtest/cmsdk-apb-timer-test.c b/tests/qtest/cmsdk-apb-timer-test.c new file mode 100644 index 0000000000..e85e1f7448 --- /dev/null +++ b/tests/qtest/cmsdk-apb-timer-test.c @@ -0,0 +1,75 @@ +/* + * QTest testcase for the CMSDK APB timer device + * + * Copyright (c) 2021 Linaro Limited + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "libqtest-single.h" + +/* IoTKit/ARMSSE-200 timer0; driven at 25MHz in mps2-an385, so 40ns per tick */ +#define TIMER_BASE 0x40000000 + +#define CTRL 0 +#define VALUE 4 +#define RELOAD 8 +#define INTSTATUS 0xc + +static void test_timer(void) +{ + g_assert_true(readl(TIMER_BASE + INTSTATUS) == 0); + + /* Start timer: will fire after 40 * 1000 == 40000 ns */ + writel(TIMER_BASE + RELOAD, 1000); + writel(TIMER_BASE + CTRL, 9); + + /* Step to just past the 500th tick and check VALUE */ + clock_step(40 * 500 + 1); + g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 0); + g_assert_cmpuint(readl(TIMER_BASE + VALUE), ==, 500); + + /* Just past the 1000th tick: timer should have fired */ + clock_step(40 * 500); + g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 1); + g_assert_cmpuint(readl(TIMER_BASE + VALUE), ==, 0); + + /* VALUE reloads at the following tick */ + clock_step(40); + g_assert_cmpuint(readl(TIMER_BASE + VALUE), ==, 1000); + + /* Check write-1-to-clear behaviour of INTSTATUS */ + writel(TIMER_BASE + INTSTATUS, 0); + g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 1); + writel(TIMER_BASE + INTSTATUS, 1); + g_assert_cmpuint(readl(TIMER_BASE + INTSTATUS), ==, 0); + + /* Turn off the timer */ + writel(TIMER_BASE + CTRL, 0); +} + +int main(int argc, char **argv) +{ + int r; + + g_test_init(&argc, &argv, NULL); + + qtest_start("-machine mps2-an385"); + + qtest_add_func("/cmsdk-apb-timer/timer", test_timer); + + r = g_test_run(); + + qtest_end(); + + return r; +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 7ccdf02311..519a40d5b8 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -142,6 +142,7 @@ qtests_npcm7xx = \ 'npcm7xx_timer-test', 'npcm7xx_watchdog_timer-test'] qtests_arm = \ + (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \ (config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \ (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \ ['arm-cpu-features', -- cgit v1.2.3 From 9cf5eb29b24d0a620127e2b0b3a92d3d6ea8991a Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 28 Jan 2021 11:41:24 +0000 Subject: tests: Add a simple test of the CMSDK APB watchdog MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a simple test of the CMSDK watchdog, since we're about to do some refactoring of how it is clocked. Signed-off-by: Peter Maydell Reviewed-by: Luc Michel Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Message-id: 20210128114145.20536-5-peter.maydell@linaro.org Message-id: 20210121190622.22000-5-peter.maydell@linaro.org Reviewed-by: Philippe Mathieu-Daudé --- tests/qtest/cmsdk-apb-watchdog-test.c | 79 +++++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 1 + 2 files changed, 80 insertions(+) create mode 100644 tests/qtest/cmsdk-apb-watchdog-test.c (limited to 'tests') diff --git a/tests/qtest/cmsdk-apb-watchdog-test.c b/tests/qtest/cmsdk-apb-watchdog-test.c new file mode 100644 index 0000000000..950f64c527 --- /dev/null +++ b/tests/qtest/cmsdk-apb-watchdog-test.c @@ -0,0 +1,79 @@ +/* + * QTest testcase for the CMSDK APB watchdog device + * + * Copyright (c) 2021 Linaro Limited + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "libqtest-single.h" + +/* + * lm3s811evb watchdog; at board startup this runs at 200MHz / 16 == 12.5MHz, + * which is 80ns per tick. + */ +#define WDOG_BASE 0x40000000 + +#define WDOGLOAD 0 +#define WDOGVALUE 4 +#define WDOGCONTROL 8 +#define WDOGINTCLR 0xc +#define WDOGRIS 0x10 +#define WDOGMIS 0x14 +#define WDOGLOCK 0xc00 + +static void test_watchdog(void) +{ + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); + + writel(WDOG_BASE + WDOGCONTROL, 1); + writel(WDOG_BASE + WDOGLOAD, 1000); + + /* Step to just past the 500th tick */ + clock_step(500 * 80 + 1); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500); + + /* Just past the 1000th tick: timer should have fired */ + clock_step(500 * 80); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 0); + + /* VALUE reloads at following tick */ + clock_step(80); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000); + + /* Writing any value to WDOGINTCLR clears the interrupt and reloads */ + clock_step(500 * 80); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1); + writel(WDOG_BASE + WDOGINTCLR, 0); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); +} + +int main(int argc, char **argv) +{ + int r; + + g_test_init(&argc, &argv, NULL); + + qtest_start("-machine lm3s811evb"); + + qtest_add_func("/cmsdk-apb-watchdog/watchdog", test_watchdog); + + r = g_test_run(); + + qtest_end(); + + return r; +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 519a40d5b8..5b10bfbcfb 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -143,6 +143,7 @@ qtests_npcm7xx = \ 'npcm7xx_watchdog_timer-test'] qtests_arm = \ (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \ + (config_all_devices.has_key('CONFIG_CMSDK_APB_WATCHDOG') ? ['cmsdk-apb-watchdog-test'] : []) + \ (config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \ (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \ ['arm-cpu-features', -- cgit v1.2.3 From 9bc064b539a3e62e077c816461da50ed9230994a Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 28 Jan 2021 11:41:25 +0000 Subject: tests: Add a simple test of the CMSDK APB dual timer MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a simple test of the CMSDK dual timer, since we're about to do some refactoring of how it is clocked. Signed-off-by: Peter Maydell Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel Message-id: 20210128114145.20536-6-peter.maydell@linaro.org Message-id: 20210121190622.22000-6-peter.maydell@linaro.org --- tests/qtest/cmsdk-apb-dualtimer-test.c | 130 +++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 1 + 2 files changed, 131 insertions(+) create mode 100644 tests/qtest/cmsdk-apb-dualtimer-test.c (limited to 'tests') diff --git a/tests/qtest/cmsdk-apb-dualtimer-test.c b/tests/qtest/cmsdk-apb-dualtimer-test.c new file mode 100644 index 0000000000..ad6a758289 --- /dev/null +++ b/tests/qtest/cmsdk-apb-dualtimer-test.c @@ -0,0 +1,130 @@ +/* + * QTest testcase for the CMSDK APB dualtimer device + * + * Copyright (c) 2021 Linaro Limited + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" +#include "libqtest-single.h" + +/* IoTKit/ARMSSE dualtimer; driven at 25MHz in mps2-an385, so 40ns per tick */ +#define TIMER_BASE 0x40002000 + +#define TIMER1LOAD 0 +#define TIMER1VALUE 4 +#define TIMER1CONTROL 8 +#define TIMER1INTCLR 0xc +#define TIMER1RIS 0x10 +#define TIMER1MIS 0x14 +#define TIMER1BGLOAD 0x18 + +#define TIMER2LOAD 0x20 +#define TIMER2VALUE 0x24 +#define TIMER2CONTROL 0x28 +#define TIMER2INTCLR 0x2c +#define TIMER2RIS 0x30 +#define TIMER2MIS 0x34 +#define TIMER2BGLOAD 0x38 + +#define CTRL_ENABLE (1 << 7) +#define CTRL_PERIODIC (1 << 6) +#define CTRL_INTEN (1 << 5) +#define CTRL_PRESCALE_1 (0 << 2) +#define CTRL_PRESCALE_16 (1 << 2) +#define CTRL_PRESCALE_256 (2 << 2) +#define CTRL_32BIT (1 << 1) +#define CTRL_ONESHOT (1 << 0) + +static void test_dualtimer(void) +{ + g_assert_true(readl(TIMER_BASE + TIMER1RIS) == 0); + + /* Start timer: will fire after 40000 ns */ + writel(TIMER_BASE + TIMER1LOAD, 1000); + /* enable in free-running, wrapping, interrupt mode */ + writel(TIMER_BASE + TIMER1CONTROL, CTRL_ENABLE | CTRL_INTEN); + + /* Step to just past the 500th tick and check VALUE */ + clock_step(500 * 40 + 1); + g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 0); + g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 500); + + /* Just past the 1000th tick: timer should have fired */ + clock_step(500 * 40); + g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 1); + g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 0); + + /* + * We are in free-running wrapping 16-bit mode, so on the following + * tick VALUE should have wrapped round to 0xffff. + */ + clock_step(40); + g_assert_cmpuint(readl(TIMER_BASE + TIMER1VALUE), ==, 0xffff); + + /* Check that any write to INTCLR clears interrupt */ + writel(TIMER_BASE + TIMER1INTCLR, 1); + g_assert_cmpuint(readl(TIMER_BASE + TIMER1RIS), ==, 0); + + /* Turn off the timer */ + writel(TIMER_BASE + TIMER1CONTROL, 0); +} + +static void test_prescale(void) +{ + g_assert_true(readl(TIMER_BASE + TIMER2RIS) == 0); + + /* Start timer: will fire after 40 * 256 * 1000 == 1024000 ns */ + writel(TIMER_BASE + TIMER2LOAD, 1000); + /* enable in periodic, wrapping, interrupt mode, prescale 256 */ + writel(TIMER_BASE + TIMER2CONTROL, + CTRL_ENABLE | CTRL_INTEN | CTRL_PERIODIC | CTRL_PRESCALE_256); + + /* Step to just past the 500th tick and check VALUE */ + clock_step(40 * 256 * 501); + g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 0); + g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 500); + + /* Just past the 1000th tick: timer should have fired */ + clock_step(40 * 256 * 500); + g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 1); + g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 0); + + /* In periodic mode the tick VALUE now reloads */ + clock_step(40 * 256); + g_assert_cmpuint(readl(TIMER_BASE + TIMER2VALUE), ==, 1000); + + /* Check that any write to INTCLR clears interrupt */ + writel(TIMER_BASE + TIMER2INTCLR, 1); + g_assert_cmpuint(readl(TIMER_BASE + TIMER2RIS), ==, 0); + + /* Turn off the timer */ + writel(TIMER_BASE + TIMER2CONTROL, 0); +} + +int main(int argc, char **argv) +{ + int r; + + g_test_init(&argc, &argv, NULL); + + qtest_start("-machine mps2-an385"); + + qtest_add_func("/cmsdk-apb-dualtimer/dualtimer", test_dualtimer); + qtest_add_func("/cmsdk-apb-dualtimer/prescale", test_prescale); + + r = g_test_run(); + + qtest_end(); + + return r; +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 5b10bfbcfb..c83bc211b6 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -142,6 +142,7 @@ qtests_npcm7xx = \ 'npcm7xx_timer-test', 'npcm7xx_watchdog_timer-test'] qtests_arm = \ + (config_all_devices.has_key('CONFIG_CMSDK_APB_DUALTIMER') ? ['cmsdk-apb-dualtimer-test'] : []) + \ (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \ (config_all_devices.has_key('CONFIG_CMSDK_APB_WATCHDOG') ? ['cmsdk-apb-watchdog-test'] : []) + \ (config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \ -- cgit v1.2.3 From 7bbb12f305c894b861229073e5d43ea80bcce6e0 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 28 Jan 2021 11:41:41 +0000 Subject: tests/qtest/cmsdk-apb-watchdog-test: Test clock changes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Now that the CMSDK APB watchdog uses its Clock input, it will correctly respond when the system clock frequency is changed using the RCC register on in the Stellaris board system registers. Test that when the RCC register is written it causes the watchdog timer to change speed. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Luc Michel Tested-by: Philippe Mathieu-Daudé Message-id: 20210128114145.20536-22-peter.maydell@linaro.org Message-id: 20210121190622.22000-22-peter.maydell@linaro.org --- tests/qtest/cmsdk-apb-watchdog-test.c | 52 +++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) (limited to 'tests') diff --git a/tests/qtest/cmsdk-apb-watchdog-test.c b/tests/qtest/cmsdk-apb-watchdog-test.c index 950f64c527..2710cb17b8 100644 --- a/tests/qtest/cmsdk-apb-watchdog-test.c +++ b/tests/qtest/cmsdk-apb-watchdog-test.c @@ -15,6 +15,7 @@ */ #include "qemu/osdep.h" +#include "qemu/bitops.h" #include "libqtest-single.h" /* @@ -31,6 +32,11 @@ #define WDOGMIS 0x14 #define WDOGLOCK 0xc00 +#define SSYS_BASE 0x400fe000 +#define RCC 0x60 +#define SYSDIV_SHIFT 23 +#define SYSDIV_LENGTH 4 + static void test_watchdog(void) { g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); @@ -61,6 +67,50 @@ static void test_watchdog(void) g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); } +static void test_clock_change(void) +{ + uint32_t rcc; + + /* + * Test that writing to the stellaris board's RCC register to + * change the system clock frequency causes the watchdog + * to change the speed it counts at. + */ + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); + + writel(WDOG_BASE + WDOGCONTROL, 1); + writel(WDOG_BASE + WDOGLOAD, 1000); + + /* Step to just past the 500th tick */ + clock_step(80 * 500 + 1); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500); + + /* Rewrite RCC.SYSDIV from 16 to 8, so the clock is now 40ns per tick */ + rcc = readl(SSYS_BASE + RCC); + g_assert_cmpuint(extract32(rcc, SYSDIV_SHIFT, SYSDIV_LENGTH), ==, 0xf); + rcc = deposit32(rcc, SYSDIV_SHIFT, SYSDIV_LENGTH, 7); + writel(SSYS_BASE + RCC, rcc); + + /* Just past the 1000th tick: timer should have fired */ + clock_step(40 * 500); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1); + + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 0); + + /* VALUE reloads at following tick */ + clock_step(41); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000); + + /* Writing any value to WDOGINTCLR clears the interrupt and reloads */ + clock_step(40 * 500); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 500); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 1); + writel(WDOG_BASE + WDOGINTCLR, 0); + g_assert_cmpuint(readl(WDOG_BASE + WDOGVALUE), ==, 1000); + g_assert_cmpuint(readl(WDOG_BASE + WDOGRIS), ==, 0); +} + int main(int argc, char **argv) { int r; @@ -70,6 +120,8 @@ int main(int argc, char **argv) qtest_start("-machine lm3s811evb"); qtest_add_func("/cmsdk-apb-watchdog/watchdog", test_watchdog); + qtest_add_func("/cmsdk-apb-watchdog/watchdog_clock_change", + test_clock_change); r = g_test_run(); -- cgit v1.2.3