From 58368113989403775496b3422f22094713703157 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marc=20Mar=C3=AD?= Date: Mon, 1 Sep 2014 12:07:59 +0200 Subject: libqos: Added MSI-X support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Added MSI-X support for qtest PCI. Added MSI-X support for virtio-pci. Added MSI-X test case in virtio-blk-test. Signed-off-by: Marc Marí Signed-off-by: Stefan Hajnoczi --- tests/libqos/pci.c | 111 +++++++++++++++++++++++++++- tests/libqos/pci.h | 10 +++ tests/libqos/virtio-pci.c | 142 +++++++++++++++++++++++++++++++----- tests/libqos/virtio-pci.h | 17 +++++ tests/libqos/virtio.c | 17 ++++- tests/libqos/virtio.h | 11 ++- tests/virtio-blk-test.c | 180 ++++++++++++++++++++++++++++++++++++---------- 7 files changed, 426 insertions(+), 62 deletions(-) (limited to 'tests') diff --git a/tests/libqos/pci.c b/tests/libqos/pci.c index ce0b308a83..d5ce683d77 100644 --- a/tests/libqos/pci.c +++ b/tests/libqos/pci.c @@ -15,8 +15,6 @@ #include "hw/pci/pci_regs.h" #include -#include - void qpci_device_foreach(QPCIBus *bus, int vendor_id, int device_id, void (*func)(QPCIDevice *dev, int devfn, void *data), void *data) @@ -75,6 +73,115 @@ void qpci_device_enable(QPCIDevice *dev) qpci_config_writew(dev, PCI_COMMAND, cmd); } +uint8_t qpci_find_capability(QPCIDevice *dev, uint8_t id) +{ + uint8_t cap; + uint8_t addr = qpci_config_readb(dev, PCI_CAPABILITY_LIST); + + do { + cap = qpci_config_readb(dev, addr); + if (cap != id) { + addr = qpci_config_readb(dev, addr + PCI_CAP_LIST_NEXT); + } + } while (cap != id && addr != 0); + + return addr; +} + +void qpci_msix_enable(QPCIDevice *dev) +{ + uint8_t addr; + uint16_t val; + uint32_t table; + uint8_t bir_table; + uint8_t bir_pba; + void *offset; + + addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX); + g_assert_cmphex(addr, !=, 0); + + val = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS); + qpci_config_writew(dev, addr + PCI_MSIX_FLAGS, val | PCI_MSIX_FLAGS_ENABLE); + + table = qpci_config_readl(dev, addr + PCI_MSIX_TABLE); + bir_table = table & PCI_MSIX_FLAGS_BIRMASK; + offset = qpci_iomap(dev, bir_table, NULL); + dev->msix_table = offset + (table & ~PCI_MSIX_FLAGS_BIRMASK); + + table = qpci_config_readl(dev, addr + PCI_MSIX_PBA); + bir_pba = table & PCI_MSIX_FLAGS_BIRMASK; + if (bir_pba != bir_table) { + offset = qpci_iomap(dev, bir_pba, NULL); + } + dev->msix_pba = offset + (table & ~PCI_MSIX_FLAGS_BIRMASK); + + g_assert(dev->msix_table != NULL); + g_assert(dev->msix_pba != NULL); + dev->msix_enabled = true; +} + +void qpci_msix_disable(QPCIDevice *dev) +{ + uint8_t addr; + uint16_t val; + + g_assert(dev->msix_enabled); + addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX); + g_assert_cmphex(addr, !=, 0); + val = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS); + qpci_config_writew(dev, addr + PCI_MSIX_FLAGS, + val & ~PCI_MSIX_FLAGS_ENABLE); + + qpci_iounmap(dev, dev->msix_table); + qpci_iounmap(dev, dev->msix_pba); + dev->msix_enabled = 0; + dev->msix_table = NULL; + dev->msix_pba = NULL; +} + +bool qpci_msix_pending(QPCIDevice *dev, uint16_t entry) +{ + uint32_t pba_entry; + uint8_t bit_n = entry % 32; + void *addr = dev->msix_pba + (entry / 32) * PCI_MSIX_ENTRY_SIZE / 4; + + g_assert(dev->msix_enabled); + pba_entry = qpci_io_readl(dev, addr); + qpci_io_writel(dev, addr, pba_entry & ~(1 << bit_n)); + return (pba_entry & (1 << bit_n)) != 0; +} + +bool qpci_msix_masked(QPCIDevice *dev, uint16_t entry) +{ + uint8_t addr; + uint16_t val; + void *vector_addr = dev->msix_table + (entry * PCI_MSIX_ENTRY_SIZE); + + g_assert(dev->msix_enabled); + addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX); + g_assert_cmphex(addr, !=, 0); + val = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS); + + if (val & PCI_MSIX_FLAGS_MASKALL) { + return true; + } else { + return (qpci_io_readl(dev, vector_addr + PCI_MSIX_ENTRY_VECTOR_CTRL) + & PCI_MSIX_ENTRY_CTRL_MASKBIT) != 0; + } +} + +uint16_t qpci_msix_table_size(QPCIDevice *dev) +{ + uint8_t addr; + uint16_t control; + + addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX); + g_assert_cmphex(addr, !=, 0); + + control = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS); + return (control & PCI_MSIX_FLAGS_QSIZE) + 1; +} + uint8_t qpci_config_readb(QPCIDevice *dev, uint8_t offset) { return dev->bus->config_readb(dev->bus, dev->devfn, offset); diff --git a/tests/libqos/pci.h b/tests/libqos/pci.h index 9ee048b154..d51eb9e219 100644 --- a/tests/libqos/pci.h +++ b/tests/libqos/pci.h @@ -14,6 +14,7 @@ #define LIBQOS_PCI_H #include +#include "libqtest.h" #define QPCI_DEVFN(dev, fn) (((dev) << 3) | (fn)) @@ -49,6 +50,9 @@ struct QPCIDevice { QPCIBus *bus; int devfn; + bool msix_enabled; + void *msix_table; + void *msix_pba; }; void qpci_device_foreach(QPCIBus *bus, int vendor_id, int device_id, @@ -57,6 +61,12 @@ void qpci_device_foreach(QPCIBus *bus, int vendor_id, int device_id, QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn); void qpci_device_enable(QPCIDevice *dev); +uint8_t qpci_find_capability(QPCIDevice *dev, uint8_t id); +void qpci_msix_enable(QPCIDevice *dev); +void qpci_msix_disable(QPCIDevice *dev); +bool qpci_msix_pending(QPCIDevice *dev, uint16_t entry); +bool qpci_msix_masked(QPCIDevice *dev, uint16_t entry); +uint16_t qpci_msix_table_size(QPCIDevice *dev); uint8_t qpci_config_readb(QPCIDevice *dev, uint8_t offset); uint16_t qpci_config_readw(QPCIDevice *dev, uint8_t offset); diff --git a/tests/libqos/virtio-pci.c b/tests/libqos/virtio-pci.c index cf15f7a45b..ab28717305 100644 --- a/tests/libqos/virtio-pci.c +++ b/tests/libqos/virtio-pci.c @@ -36,6 +36,8 @@ static QVirtioPCIDevice *qpcidevice_to_qvirtiodevice(QPCIDevice *pdev) qpci_config_readw(vpcidev->pdev, PCI_SUBSYSTEM_ID); } + vpcidev->config_msix_entry = -1; + return vpcidev; } @@ -125,10 +127,45 @@ static void qvirtio_pci_set_status(QVirtioDevice *d, uint8_t status) qpci_io_writeb(dev->pdev, dev->addr + QVIRTIO_DEVICE_STATUS, status); } -static uint8_t qvirtio_pci_get_isr_status(QVirtioDevice *d) +static bool qvirtio_pci_get_queue_isr_status(QVirtioDevice *d, QVirtQueue *vq) { QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d; - return qpci_io_readb(dev->pdev, dev->addr + QVIRTIO_ISR_STATUS); + QVirtQueuePCI *vqpci = (QVirtQueuePCI *)vq; + uint32_t data; + + if (dev->pdev->msix_enabled) { + g_assert_cmpint(vqpci->msix_entry, !=, -1); + if (qpci_msix_masked(dev->pdev, vqpci->msix_entry)) { + /* No ISR checking should be done if masked, but read anyway */ + return qpci_msix_pending(dev->pdev, vqpci->msix_entry); + } else { + data = readl(vqpci->msix_addr); + writel(vqpci->msix_addr, 0); + return data == vqpci->msix_data; + } + } else { + return qpci_io_readb(dev->pdev, dev->addr + QVIRTIO_ISR_STATUS) & 1; + } +} + +static bool qvirtio_pci_get_config_isr_status(QVirtioDevice *d) +{ + QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d; + uint32_t data; + + if (dev->pdev->msix_enabled) { + g_assert_cmpint(dev->config_msix_entry, !=, -1); + if (qpci_msix_masked(dev->pdev, dev->config_msix_entry)) { + /* No ISR checking should be done if masked, but read anyway */ + return qpci_msix_pending(dev->pdev, dev->config_msix_entry); + } else { + data = readl(dev->config_msix_addr); + writel(dev->config_msix_addr, 0); + return data == dev->config_msix_data; + } + } else { + return qpci_io_readb(dev->pdev, dev->addr + QVIRTIO_ISR_STATUS) & 2; + } } static void qvirtio_pci_queue_select(QVirtioDevice *d, uint16_t index) @@ -154,32 +191,34 @@ static QVirtQueue *qvirtio_pci_virtqueue_setup(QVirtioDevice *d, { uint32_t feat; uint64_t addr; - QVirtQueue *vq; + QVirtQueuePCI *vqpci; - vq = g_malloc0(sizeof(*vq)); + vqpci = g_malloc0(sizeof(*vqpci)); feat = qvirtio_pci_get_guest_features(d); qvirtio_pci_queue_select(d, index); - vq->index = index; - vq->size = qvirtio_pci_get_queue_size(d); - vq->free_head = 0; - vq->num_free = vq->size; - vq->align = QVIRTIO_PCI_ALIGN; - vq->indirect = (feat & QVIRTIO_F_RING_INDIRECT_DESC) != 0; + vqpci->vq.index = index; + vqpci->vq.size = qvirtio_pci_get_queue_size(d); + vqpci->vq.free_head = 0; + vqpci->vq.num_free = vqpci->vq.size; + vqpci->vq.align = QVIRTIO_PCI_ALIGN; + vqpci->vq.indirect = (feat & QVIRTIO_F_RING_INDIRECT_DESC) != 0; + + vqpci->msix_entry = -1; + vqpci->msix_addr = 0; + vqpci->msix_data = 0x12345678; /* Check different than 0 */ - g_assert_cmpint(vq->size, !=, 0); + g_assert_cmpint(vqpci->vq.size, !=, 0); /* Check power of 2 */ - g_assert_cmpint(vq->size & (vq->size - 1), ==, 0); - - addr = guest_alloc(alloc, qvring_size(vq->size, QVIRTIO_PCI_ALIGN)); - qvring_init(alloc, vq, addr); - qvirtio_pci_set_queue_address(d, vq->desc / QVIRTIO_PCI_ALIGN); + g_assert_cmpint(vqpci->vq.size & (vqpci->vq.size - 1), ==, 0); - /* TODO: MSI-X configuration */ + addr = guest_alloc(alloc, qvring_size(vqpci->vq.size, QVIRTIO_PCI_ALIGN)); + qvring_init(alloc, &vqpci->vq, addr); + qvirtio_pci_set_queue_address(d, vqpci->vq.desc / QVIRTIO_PCI_ALIGN); - return vq; + return &vqpci->vq; } static void qvirtio_pci_virtqueue_kick(QVirtioDevice *d, QVirtQueue *vq) @@ -198,7 +237,8 @@ const QVirtioBus qvirtio_pci = { .get_guest_features = qvirtio_pci_get_guest_features, .get_status = qvirtio_pci_get_status, .set_status = qvirtio_pci_set_status, - .get_isr_status = qvirtio_pci_get_isr_status, + .get_queue_isr_status = qvirtio_pci_get_queue_isr_status, + .get_config_isr_status = qvirtio_pci_get_config_isr_status, .queue_select = qvirtio_pci_queue_select, .get_queue_size = qvirtio_pci_get_queue_size, .set_queue_address = qvirtio_pci_set_queue_address, @@ -235,4 +275,68 @@ void qvirtio_pci_device_enable(QVirtioPCIDevice *d) void qvirtio_pci_device_disable(QVirtioPCIDevice *d) { qpci_iounmap(d->pdev, d->addr); + d->addr = NULL; +} + +void qvirtqueue_pci_msix_setup(QVirtioPCIDevice *d, QVirtQueuePCI *vqpci, + QGuestAllocator *alloc, uint16_t entry) +{ + uint16_t vector; + uint32_t control; + void *addr; + + g_assert(d->pdev->msix_enabled); + addr = d->pdev->msix_table + (entry * 16); + + g_assert_cmpint(entry, >=, 0); + g_assert_cmpint(entry, <, qpci_msix_table_size(d->pdev)); + vqpci->msix_entry = entry; + + vqpci->msix_addr = guest_alloc(alloc, 4); + qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_LOWER_ADDR, + vqpci->msix_addr & ~0UL); + qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_UPPER_ADDR, + (vqpci->msix_addr >> 32) & ~0UL); + qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_DATA, vqpci->msix_data); + + control = qpci_io_readl(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL); + qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL, + control & ~PCI_MSIX_ENTRY_CTRL_MASKBIT); + + qvirtio_pci_queue_select(&d->vdev, vqpci->vq.index); + qpci_io_writew(d->pdev, d->addr + QVIRTIO_MSIX_QUEUE_VECTOR, entry); + vector = qpci_io_readw(d->pdev, d->addr + QVIRTIO_MSIX_QUEUE_VECTOR); + g_assert_cmphex(vector, !=, QVIRTIO_MSI_NO_VECTOR); +} + +void qvirtio_pci_set_msix_configuration_vector(QVirtioPCIDevice *d, + QGuestAllocator *alloc, uint16_t entry) +{ + uint16_t vector; + uint32_t control; + void *addr; + + g_assert(d->pdev->msix_enabled); + addr = d->pdev->msix_table + (entry * 16); + + g_assert_cmpint(entry, >=, 0); + g_assert_cmpint(entry, <, qpci_msix_table_size(d->pdev)); + d->config_msix_entry = entry; + + d->config_msix_data = 0x12345678; + d->config_msix_addr = guest_alloc(alloc, 4); + + qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_LOWER_ADDR, + d->config_msix_addr & ~0UL); + qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_UPPER_ADDR, + (d->config_msix_addr >> 32) & ~0UL); + qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_DATA, d->config_msix_data); + + control = qpci_io_readl(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL); + qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL, + control & ~PCI_MSIX_ENTRY_CTRL_MASKBIT); + + qpci_io_writew(d->pdev, d->addr + QVIRTIO_MSIX_CONF_VECTOR, entry); + vector = qpci_io_readw(d->pdev, d->addr + QVIRTIO_MSIX_CONF_VECTOR); + g_assert_cmphex(vector, !=, QVIRTIO_MSI_NO_VECTOR); } diff --git a/tests/libqos/virtio-pci.h b/tests/libqos/virtio-pci.h index 40bd12db13..883f7ff267 100644 --- a/tests/libqos/virtio-pci.h +++ b/tests/libqos/virtio-pci.h @@ -28,12 +28,24 @@ #define QVIRTIO_PCI_ALIGN 4096 +#define QVIRTIO_MSI_NO_VECTOR 0xFFFF + typedef struct QVirtioPCIDevice { QVirtioDevice vdev; QPCIDevice *pdev; void *addr; + uint16_t config_msix_entry; + uint64_t config_msix_addr; + uint32_t config_msix_data; } QVirtioPCIDevice; +typedef struct QVirtQueuePCI { + QVirtQueue vq; + uint16_t msix_entry; + uint64_t msix_addr; + uint32_t msix_data; +} QVirtQueuePCI; + extern const QVirtioBus qvirtio_pci; void qvirtio_pci_foreach(QPCIBus *bus, uint16_t device_type, @@ -41,4 +53,9 @@ void qvirtio_pci_foreach(QPCIBus *bus, uint16_t device_type, QVirtioPCIDevice *qvirtio_pci_device_find(QPCIBus *bus, uint16_t device_type); void qvirtio_pci_device_enable(QVirtioPCIDevice *d); void qvirtio_pci_device_disable(QVirtioPCIDevice *d); + +void qvirtio_pci_set_msix_configuration_vector(QVirtioPCIDevice *d, + QGuestAllocator *alloc, uint16_t entry); +void qvirtqueue_pci_msix_setup(QVirtioPCIDevice *d, QVirtQueuePCI *vqpci, + QGuestAllocator *alloc, uint16_t entry); #endif diff --git a/tests/libqos/virtio.c b/tests/libqos/virtio.c index b1cab1f699..16eaf79425 100644 --- a/tests/libqos/virtio.c +++ b/tests/libqos/virtio.c @@ -78,12 +78,25 @@ void qvirtio_set_driver_ok(const QVirtioBus *bus, QVirtioDevice *d) QVIRTIO_DRIVER_OK | QVIRTIO_DRIVER | QVIRTIO_ACKNOWLEDGE); } -bool qvirtio_wait_isr(const QVirtioBus *bus, QVirtioDevice *d, uint8_t mask, +bool qvirtio_wait_queue_isr(const QVirtioBus *bus, QVirtioDevice *d, + QVirtQueue *vq, uint64_t timeout) +{ + do { + clock_step(10); + if (bus->get_queue_isr_status(d, vq)) { + break; /* It has ended */ + } + } while (--timeout); + + return timeout != 0; +} + +bool qvirtio_wait_config_isr(const QVirtioBus *bus, QVirtioDevice *d, uint64_t timeout) { do { clock_step(10); - if (bus->get_isr_status(d) & mask) { + if (bus->get_config_isr_status(d)) { break; /* It has ended */ } } while (--timeout); diff --git a/tests/libqos/virtio.h b/tests/libqos/virtio.h index 1860660dfd..cebccd21d1 100644 --- a/tests/libqos/virtio.h +++ b/tests/libqos/virtio.h @@ -109,8 +109,11 @@ typedef struct QVirtioBus { /* Set status of the device */ void (*set_status)(QVirtioDevice *d, uint8_t status); - /* Get the ISR status of the device */ - uint8_t (*get_isr_status)(QVirtioDevice *d); + /* Get the queue ISR status of the device */ + bool (*get_queue_isr_status)(QVirtioDevice *d, QVirtQueue *vq); + + /* Get the configuration ISR status of the device */ + bool (*get_config_isr_status)(QVirtioDevice *d); /* Select a queue to work on */ void (*queue_select)(QVirtioDevice *d, uint16_t index); @@ -153,7 +156,9 @@ void qvirtio_set_acknowledge(const QVirtioBus *bus, QVirtioDevice *d); void qvirtio_set_driver(const QVirtioBus *bus, QVirtioDevice *d); void qvirtio_set_driver_ok(const QVirtioBus *bus, QVirtioDevice *d); -bool qvirtio_wait_isr(const QVirtioBus *bus, QVirtioDevice *d, uint8_t mask, +bool qvirtio_wait_queue_isr(const QVirtioBus *bus, QVirtioDevice *d, + QVirtQueue *vq, uint64_t timeout); +bool qvirtio_wait_config_isr(const QVirtioBus *bus, QVirtioDevice *d, uint64_t timeout); QVirtQueue *qvirtqueue_setup(const QVirtioBus *bus, QVirtioDevice *d, QGuestAllocator *alloc, uint16_t index); diff --git a/tests/virtio-blk-test.c b/tests/virtio-blk-test.c index 672580b206..0100aaa950 100644 --- a/tests/virtio-blk-test.c +++ b/tests/virtio-blk-test.c @@ -134,7 +134,7 @@ static void pci_basic(void) { QVirtioPCIDevice *dev; QPCIBus *bus; - QVirtQueue *vq; + QVirtQueuePCI *vqpci; QGuestAllocator *alloc; QVirtioBlkReq req; void *addr; @@ -162,7 +162,8 @@ static void pci_basic(void) qvirtio_set_features(&qvirtio_pci, &dev->vdev, features); alloc = pc_alloc_init(); - vq = qvirtqueue_setup(&qvirtio_pci, &dev->vdev, alloc, 0); + vqpci = (QVirtQueuePCI *)qvirtqueue_setup(&qvirtio_pci, &dev->vdev, + alloc, 0); qvirtio_set_driver_ok(&qvirtio_pci, &dev->vdev); @@ -178,11 +179,11 @@ static void pci_basic(void) g_free(req.data); - free_head = qvirtqueue_add(vq, req_addr, 528, false, true); - qvirtqueue_add(vq, req_addr + 528, 1, true, false); - qvirtqueue_kick(&qvirtio_pci, &dev->vdev, vq, free_head); + free_head = qvirtqueue_add(&vqpci->vq, req_addr, 528, false, true); + qvirtqueue_add(&vqpci->vq, req_addr + 528, 1, true, false); + qvirtqueue_kick(&qvirtio_pci, &dev->vdev, &vqpci->vq, free_head); - g_assert(qvirtio_wait_isr(&qvirtio_pci, &dev->vdev, 0x1, + g_assert(qvirtio_wait_queue_isr(&qvirtio_pci, &dev->vdev, &vqpci->vq, QVIRTIO_BLK_TIMEOUT)); status = readb(req_addr + 528); g_assert_cmpint(status, ==, 0); @@ -199,12 +200,12 @@ static void pci_basic(void) g_free(req.data); - free_head = qvirtqueue_add(vq, req_addr, 16, false, true); - qvirtqueue_add(vq, req_addr + 16, 513, true, false); + free_head = qvirtqueue_add(&vqpci->vq, req_addr, 16, false, true); + qvirtqueue_add(&vqpci->vq, req_addr + 16, 513, true, false); - qvirtqueue_kick(&qvirtio_pci, &dev->vdev, vq, free_head); + qvirtqueue_kick(&qvirtio_pci, &dev->vdev, &vqpci->vq, free_head); - g_assert(qvirtio_wait_isr(&qvirtio_pci, &dev->vdev, 0x1, + g_assert(qvirtio_wait_queue_isr(&qvirtio_pci, &dev->vdev, &vqpci->vq, QVIRTIO_BLK_TIMEOUT)); status = readb(req_addr + 528); g_assert_cmpint(status, ==, 0); @@ -226,15 +227,13 @@ static void pci_basic(void) req_addr = virtio_blk_request(alloc, &req, 512); - g_free(req.data); - - free_head = qvirtqueue_add(vq, req_addr, 16, false, true); - qvirtqueue_add(vq, req_addr + 16, 512, false, true); - qvirtqueue_add(vq, req_addr + 528, 1, true, false); + free_head = qvirtqueue_add(&vqpci->vq, req_addr, 16, false, true); + qvirtqueue_add(&vqpci->vq, req_addr + 16, 512, false, true); + qvirtqueue_add(&vqpci->vq, req_addr + 528, 1, true, false); - qvirtqueue_kick(&qvirtio_pci, &dev->vdev, vq, free_head); + qvirtqueue_kick(&qvirtio_pci, &dev->vdev, &vqpci->vq, free_head); - g_assert(qvirtio_wait_isr(&qvirtio_pci, &dev->vdev, 0x1, + g_assert(qvirtio_wait_queue_isr(&qvirtio_pci, &dev->vdev, &vqpci->vq, QVIRTIO_BLK_TIMEOUT)); status = readb(req_addr + 528); g_assert_cmpint(status, ==, 0); @@ -251,19 +250,17 @@ static void pci_basic(void) g_free(req.data); - free_head = qvirtqueue_add(vq, req_addr, 16, false, true); - qvirtqueue_add(vq, req_addr + 16, 512, true, true); - qvirtqueue_add(vq, req_addr + 528, 1, true, false); + free_head = qvirtqueue_add(&vqpci->vq, req_addr, 16, false, true); + qvirtqueue_add(&vqpci->vq, req_addr + 16, 512, true, true); + qvirtqueue_add(&vqpci->vq, req_addr + 528, 1, true, false); - qvirtqueue_kick(&qvirtio_pci, &dev->vdev, vq, free_head); + qvirtqueue_kick(&qvirtio_pci, &dev->vdev, &vqpci->vq, free_head); - g_assert(qvirtio_wait_isr(&qvirtio_pci, &dev->vdev, 0x1, + g_assert(qvirtio_wait_queue_isr(&qvirtio_pci, &dev->vdev, &vqpci->vq, QVIRTIO_BLK_TIMEOUT)); status = readb(req_addr + 528); g_assert_cmpint(status, ==, 0); - guest_free(alloc, req_addr); - data = g_malloc0(512); memread(req_addr + 16, data, 512); g_assert_cmpstr(data, ==, "TEST"); @@ -272,7 +269,7 @@ static void pci_basic(void) guest_free(alloc, req_addr); /* End test */ - guest_free(alloc, vq->desc); + guest_free(alloc, vqpci->vq.desc); qvirtio_pci_device_disable(dev); g_free(dev); test_end(); @@ -282,7 +279,7 @@ static void pci_indirect(void) { QVirtioPCIDevice *dev; QPCIBus *bus; - QVirtQueue *vq; + QVirtQueuePCI *vqpci; QGuestAllocator *alloc; QVirtioBlkReq req; QVRingIndirectDesc *indirect; @@ -311,8 +308,8 @@ static void pci_indirect(void) qvirtio_set_features(&qvirtio_pci, &dev->vdev, features); alloc = pc_alloc_init(); - vq = qvirtqueue_setup(&qvirtio_pci, &dev->vdev, alloc, 0); - + vqpci = (QVirtQueuePCI *)qvirtqueue_setup(&qvirtio_pci, &dev->vdev, + alloc, 0); qvirtio_set_driver_ok(&qvirtio_pci, &dev->vdev); /* Write request */ @@ -329,10 +326,10 @@ static void pci_indirect(void) indirect = qvring_indirect_desc_setup(&dev->vdev, alloc, 2); qvring_indirect_desc_add(indirect, req_addr, 528, false); qvring_indirect_desc_add(indirect, req_addr + 528, 1, true); - free_head = qvirtqueue_add_indirect(vq, indirect); - qvirtqueue_kick(&qvirtio_pci, &dev->vdev, vq, free_head); + free_head = qvirtqueue_add_indirect(&vqpci->vq, indirect); + qvirtqueue_kick(&qvirtio_pci, &dev->vdev, &vqpci->vq, free_head); - g_assert(qvirtio_wait_isr(&qvirtio_pci, &dev->vdev, 0x1, + g_assert(qvirtio_wait_queue_isr(&qvirtio_pci, &dev->vdev, &vqpci->vq, QVIRTIO_BLK_TIMEOUT)); status = readb(req_addr + 528); g_assert_cmpint(status, ==, 0); @@ -354,10 +351,10 @@ static void pci_indirect(void) indirect = qvring_indirect_desc_setup(&dev->vdev, alloc, 2); qvring_indirect_desc_add(indirect, req_addr, 16, false); qvring_indirect_desc_add(indirect, req_addr + 16, 513, true); - free_head = qvirtqueue_add_indirect(vq, indirect); - qvirtqueue_kick(&qvirtio_pci, &dev->vdev, vq, free_head); + free_head = qvirtqueue_add_indirect(&vqpci->vq, indirect); + qvirtqueue_kick(&qvirtio_pci, &dev->vdev, &vqpci->vq, free_head); - g_assert(qvirtio_wait_isr(&qvirtio_pci, &dev->vdev, 0x1, + g_assert(qvirtio_wait_queue_isr(&qvirtio_pci, &dev->vdev, &vqpci->vq, QVIRTIO_BLK_TIMEOUT)); status = readb(req_addr + 528); g_assert_cmpint(status, ==, 0); @@ -371,7 +368,7 @@ static void pci_indirect(void) guest_free(alloc, req_addr); /* End test */ - guest_free(alloc, vq->desc); + guest_free(alloc, vqpci->vq.desc); qvirtio_pci_device_disable(dev); g_free(dev); test_end(); @@ -399,7 +396,7 @@ static void pci_config(void) qmp("{ 'execute': 'block_resize', 'arguments': { 'device': 'drive0', " " 'size': %d } }", n_size); - g_assert(qvirtio_wait_isr(&qvirtio_pci, &dev->vdev, 0x2, + g_assert(qvirtio_wait_config_isr(&qvirtio_pci, &dev->vdev, QVIRTIO_BLK_TIMEOUT)); capacity = qvirtio_config_readq(&qvirtio_pci, &dev->vdev, addr); @@ -410,6 +407,116 @@ static void pci_config(void) test_end(); } +static void pci_msix(void) +{ + QVirtioPCIDevice *dev; + QPCIBus *bus; + QVirtQueuePCI *vqpci; + QGuestAllocator *alloc; + QVirtioBlkReq req; + int n_size = TEST_IMAGE_SIZE / 2; + void *addr; + uint64_t req_addr; + uint64_t capacity; + uint32_t features; + uint32_t free_head; + uint8_t status; + char *data; + + bus = test_start(); + alloc = pc_alloc_init(); + + dev = virtio_blk_init(bus); + qpci_msix_enable(dev->pdev); + + qvirtio_pci_set_msix_configuration_vector(dev, alloc, 0); + + /* MSI-X is enabled */ + addr = dev->addr + QVIRTIO_DEVICE_SPECIFIC_MSIX; + + capacity = qvirtio_config_readq(&qvirtio_pci, &dev->vdev, addr); + g_assert_cmpint(capacity, ==, TEST_IMAGE_SIZE / 512); + + features = qvirtio_get_features(&qvirtio_pci, &dev->vdev); + features = features & ~(QVIRTIO_F_BAD_FEATURE | + QVIRTIO_F_RING_INDIRECT_DESC | + QVIRTIO_F_RING_EVENT_IDX | QVIRTIO_BLK_F_SCSI); + qvirtio_set_features(&qvirtio_pci, &dev->vdev, features); + + vqpci = (QVirtQueuePCI *)qvirtqueue_setup(&qvirtio_pci, &dev->vdev, + alloc, 0); + qvirtqueue_pci_msix_setup(dev, vqpci, alloc, 1); + + qvirtio_set_driver_ok(&qvirtio_pci, &dev->vdev); + + qmp("{ 'execute': 'block_resize', 'arguments': { 'device': 'drive0', " + " 'size': %d } }", n_size); + + g_assert(qvirtio_wait_config_isr(&qvirtio_pci, &dev->vdev, + QVIRTIO_BLK_TIMEOUT)); + + capacity = qvirtio_config_readq(&qvirtio_pci, &dev->vdev, addr); + g_assert_cmpint(capacity, ==, n_size / 512); + + /* Write request */ + req.type = QVIRTIO_BLK_T_OUT; + req.ioprio = 1; + req.sector = 0; + req.data = g_malloc0(512); + strcpy(req.data, "TEST"); + + req_addr = virtio_blk_request(alloc, &req, 512); + + g_free(req.data); + + free_head = qvirtqueue_add(&vqpci->vq, req_addr, 528, false, true); + qvirtqueue_add(&vqpci->vq, req_addr + 528, 1, true, false); + qvirtqueue_kick(&qvirtio_pci, &dev->vdev, &vqpci->vq, free_head); + + g_assert(qvirtio_wait_queue_isr(&qvirtio_pci, &dev->vdev, &vqpci->vq, + QVIRTIO_BLK_TIMEOUT)); + + status = readb(req_addr + 528); + g_assert_cmpint(status, ==, 0); + + guest_free(alloc, req_addr); + + /* Read request */ + req.type = QVIRTIO_BLK_T_IN; + req.ioprio = 1; + req.sector = 0; + req.data = g_malloc0(512); + + req_addr = virtio_blk_request(alloc, &req, 512); + + g_free(req.data); + + free_head = qvirtqueue_add(&vqpci->vq, req_addr, 16, false, true); + qvirtqueue_add(&vqpci->vq, req_addr + 16, 513, true, false); + + qvirtqueue_kick(&qvirtio_pci, &dev->vdev, &vqpci->vq, free_head); + + g_assert(qvirtio_wait_queue_isr(&qvirtio_pci, &dev->vdev, &vqpci->vq, + QVIRTIO_BLK_TIMEOUT)); + + status = readb(req_addr + 528); + g_assert_cmpint(status, ==, 0); + + data = g_malloc0(512); + memread(req_addr + 16, data, 512); + g_assert_cmpstr(data, ==, "TEST"); + g_free(data); + + guest_free(alloc, req_addr); + + /* End test */ + guest_free(alloc, vqpci->vq.desc); + qpci_msix_disable(dev->pdev); + qvirtio_pci_device_disable(dev); + g_free(dev); + test_end(); +} + int main(int argc, char **argv) { int ret; @@ -419,6 +526,7 @@ int main(int argc, char **argv) g_test_add_func("/virtio/blk/pci/basic", pci_basic); g_test_add_func("/virtio/blk/pci/indirect", pci_indirect); g_test_add_func("/virtio/blk/pci/config", pci_config); + g_test_add_func("/virtio/blk/pci/msix", pci_msix); ret = g_test_run(); -- cgit v1.2.3