From d70080c4e37fc533fa10904b286f29449decc6f8 Mon Sep 17 00:00:00 2001 From: Jia Liu Date: Wed, 24 Oct 2012 22:17:13 +0800 Subject: target-mips: Add ASE DSP testcases Add MIPS ASE DSP testcases. Signed-off-by: Jia Liu Signed-off-by: Aurelien Jarno --- tests/tcg/mips/mips32-dspr2/mulq_s_w.c | 36 ++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 tests/tcg/mips/mips32-dspr2/mulq_s_w.c (limited to 'tests/tcg/mips/mips32-dspr2/mulq_s_w.c') diff --git a/tests/tcg/mips/mips32-dspr2/mulq_s_w.c b/tests/tcg/mips/mips32-dspr2/mulq_s_w.c new file mode 100644 index 0000000000..df148b7ffb --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/mulq_s_w.c @@ -0,0 +1,36 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x80001234; + rt = 0x80004321; + result = 0x80005555; + + __asm + ("mulq_s.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + + rs = 0x80000000; + rt = 0x80000000; + result = 0x7FFFFFFF; + resultdsp = 1; + + __asm + ("mulq_s.w %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); + + return 0; +} -- cgit v1.2.3