From cf0ed30eb10c7341fd1f253446e3bbb6e0114c30 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 12 Oct 2023 20:45:36 -0700 Subject: tcg/riscv: Do not reserve TCG_GUEST_BASE_REG for guest_base zero Fixes: 92c041c59b ("tcg/riscv: Add the prologue generation and register the JIT") Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'tcg') diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index d6dbcaf3cb..dc71f829d1 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -2076,8 +2076,10 @@ static void tcg_target_qemu_prologue(TCGContext *s) } #if !defined(CONFIG_SOFTMMU) - tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); - tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); + if (guest_base) { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); + tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); + } #endif /* Call generated code */ -- cgit v1.2.3