From 868314358ea3f3009fb72d2867dc73af54338ae7 Mon Sep 17 00:00:00 2001 From: pbrook Date: Sun, 11 May 2008 12:22:01 +0000 Subject: Add zero extension (pseudo-)ops. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4424 c046a42c-6fe2-441c-8c8c-71466251a162 --- tcg/README | 5 ++++- tcg/tcg-op.h | 47 ++++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 50 insertions(+), 2 deletions(-) (limited to 'tcg') diff --git a/tcg/README b/tcg/README index c27c5abed9..c47d3b07ac 100644 --- a/tcg/README +++ b/tcg/README @@ -260,10 +260,13 @@ t0 = t1 Move t1 to t0 (both operands must have the same type). * ext8s_i32/i64 t0, t1 +ext8u_i32/i64 t0, t1 ext16s_i32/i64 t0, t1 +ext16u_i32/i64 t0, t1 ext32s_i64 t0, t1 +ext32u_i64 t0, t1 -8, 16 or 32 bit sign extension (both operands must have the same type) +8, 16 or 32 bit sign/zero extension (both operands must have the same type) * bswap16_i32 t0, t1 diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 1daf130f17..8ab9536603 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -980,6 +980,18 @@ static inline void tcg_gen_ext16s_i32(TCGv ret, TCGv arg) #endif } +/* These are currently just for convenience. + We assume a target will recognise these automatically . */ +static inline void tcg_gen_ext8u_i32(TCGv ret, TCGv arg) +{ + tcg_gen_andi_i32(ret, arg, 0xffu); +} + +static inline void tcg_gen_ext16u_i32(TCGv ret, TCGv arg) +{ + tcg_gen_andi_i32(ret, arg, 0xffffu); +} + /* Note: we assume the two high bytes are set to zero */ static inline void tcg_gen_bswap16_i32(TCGv ret, TCGv arg) { @@ -1040,6 +1052,24 @@ static inline void tcg_gen_ext32s_i64(TCGv ret, TCGv arg) tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31); } +static inline void tcg_gen_ext8u_i64(TCGv ret, TCGv arg) +{ + tcg_gen_ext8u_i32(ret, arg); + tcg_gen_movi_i32(TCGV_HIGH(ret), 0); +} + +static inline void tcg_gen_ext16u_i64(TCGv ret, TCGv arg) +{ + tcg_gen_ext16u_i32(ret, arg); + tcg_gen_movi_i32(TCGV_HIGH(ret), 0); +} + +static inline void tcg_gen_ext32u_i64(TCGv ret, TCGv arg) +{ + tcg_gen_mov_i32(ret, arg); + tcg_gen_movi_i32(TCGV_HIGH(ret), 0); +} + static inline void tcg_gen_trunc_i64_i32(TCGv ret, TCGv arg) { tcg_gen_mov_i32(ret, arg); @@ -1100,6 +1130,21 @@ static inline void tcg_gen_ext32s_i64(TCGv ret, TCGv arg) #endif } +static inline void tcg_gen_ext8u_i64(TCGv ret, TCGv arg) +{ + tcg_gen_andi_i64(ret, arg, 0xffu); +} + +static inline void tcg_gen_ext16u_i64(TCGv ret, TCGv arg) +{ + tcg_gen_andi_i64(ret, arg, 0xffffu); +} + +static inline void tcg_gen_ext32u_i64(TCGv ret, TCGv arg) +{ + tcg_gen_andi_i64(ret, arg, 0xffffffffu); +} + /* Note: we assume the target supports move between 32 and 64 bit registers. This will probably break MIPS64 targets. */ static inline void tcg_gen_trunc_i64_i32(TCGv ret, TCGv arg) @@ -1111,7 +1156,7 @@ static inline void tcg_gen_trunc_i64_i32(TCGv ret, TCGv arg) registers */ static inline void tcg_gen_extu_i32_i64(TCGv ret, TCGv arg) { - tcg_gen_andi_i64(ret, arg, 0xffffffff); + tcg_gen_andi_i64(ret, arg, 0xffffffffu); } /* Note: we assume the target supports move between 32 and 64 bit -- cgit v1.2.3