From fbef2cc80fbc7836447d5b3d4741c4d15a144ec1 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Mon, 14 Apr 2014 18:10:11 +0000 Subject: tcg-mips: Convert to new_ldst Reviewed-by: Paolo Bonzini Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tcg/mips/tcg-target.h') diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index c6d2267d77..7509fa1426 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -120,7 +120,7 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_ext16s_i32 use_mips32r2_instructions #define TCG_TARGET_HAS_rot_i32 use_mips32r2_instructions -#define TCG_TARGET_HAS_new_ldst 0 +#define TCG_TARGET_HAS_new_ldst 1 /* optional instructions automatically implemented */ #define TCG_TARGET_HAS_neg_i32 0 /* sub rd, zero, rt */ -- cgit v1.2.3 From 418839044e7ab7d0282f8685f8db40bd6cd97b96 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 15 Apr 2014 09:03:59 -0700 Subject: tcg-mips: Rearrange register allocation Use FP (also known as S8) as a normal call-saved register. Include T0 in the allocation order and call-clobbered list even though it's currently used as a TCG temporary. Put the argument registers at the end of the allocation order. Reviewed-by: Paolo Bonzini Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'tcg/mips/tcg-target.h') diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 7509fa1426..c959d1c959 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -60,8 +60,11 @@ typedef enum { TCG_REG_K1, TCG_REG_GP, TCG_REG_SP, - TCG_REG_FP, + TCG_REG_S8, TCG_REG_RA, + + TCG_REG_CALL_STACK = TCG_REG_SP, + TCG_AREG0 = TCG_REG_S0, } TCGReg; #define TCG_CT_CONST_ZERO 0x100 @@ -69,7 +72,6 @@ typedef enum { #define TCG_CT_CONST_S16 0x400 /* used for function call generation */ -#define TCG_REG_CALL_STACK TCG_REG_SP #define TCG_TARGET_STACK_ALIGN 8 #define TCG_TARGET_CALL_STACK_OFFSET 16 #define TCG_TARGET_CALL_ALIGN_ARGS 1 @@ -127,8 +129,6 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_ext8u_i32 0 /* andi rt, rs, 0xff */ #define TCG_TARGET_HAS_ext16u_i32 0 /* andi rt, rs, 0xffff */ -#define TCG_AREG0 TCG_REG_S0 - #ifdef __OpenBSD__ #include #else -- cgit v1.2.3 From 1c4182687e20a4255ea827fe05081578d9c518f9 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 15 Apr 2014 09:27:40 -0700 Subject: tcg-mips: Use EXT for AND on mips32r2 At the same time, tidy deposit by introducing tcg_out_opc_bf. Reviewed-by: Paolo Bonzini Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'tcg/mips/tcg-target.h') diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index c959d1c959..b5face8b4d 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -67,10 +67,6 @@ typedef enum { TCG_AREG0 = TCG_REG_S0, } TCGReg; -#define TCG_CT_CONST_ZERO 0x100 -#define TCG_CT_CONST_U16 0x200 -#define TCG_CT_CONST_S16 0x400 - /* used for function call generation */ #define TCG_TARGET_STACK_ALIGN 8 #define TCG_TARGET_CALL_STACK_OFFSET 16 -- cgit v1.2.3