From 000cf4777aadda69d14a6994ca0d195a36733cbd Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Mon, 3 May 2021 16:47:52 -0700 Subject: tcg/arm: Add host vector framework Add registers and function stubs. The functionality is disabled via use_neon_instructions defined to 0. We must still include results for the mandatory opcodes in tcg_target_op_def, as all opcodes are checked during tcg init. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.opc.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 tcg/arm/tcg-target.opc.h (limited to 'tcg/arm/tcg-target.opc.h') diff --git a/tcg/arm/tcg-target.opc.h b/tcg/arm/tcg-target.opc.h new file mode 100644 index 0000000000..7a4578e9b4 --- /dev/null +++ b/tcg/arm/tcg-target.opc.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2019 Linaro + * + * This work is licensed under the terms of the GNU GPL, version 2 or + * (at your option) any later version. + * + * See the COPYING file in the top-level directory for details. + * + * Target-specific opcodes for host vector expansion. These will be + * emitted by tcg_expand_vec_op. For those familiar with GCC internals, + * consider these to be UNSPEC with names. + */ -- cgit v1.2.3