From bc9888f759baa64ab6084e4dd8e24ba80b0c3143 Mon Sep 17 00:00:00 2001 From: Greg Kurz Date: Mon, 16 Dec 2019 16:01:18 +0100 Subject: cpu: Use cpu_class_set_parent_reset() Convert all targets to use cpu_class_set_parent_reset() with the following coccinelle script: @@ type CPUParentClass; CPUParentClass *pcc; CPUClass *cc; identifier parent_fn; identifier child_fn; @@ +cpu_class_set_parent_reset(cc, child_fn, &pcc->parent_fn); -pcc->parent_fn = cc->reset; ... -cc->reset = child_fn; Signed-off-by: Greg Kurz Acked-by: David Gibson Reviewed-by: Alistair Francis Reviewed-by: Cornelia Huck Acked-by: David Hildenbrand Message-Id: <157650847817.354886.7047137349018460524.stgit@bahia.lan> Signed-off-by: Paolo Bonzini --- target/arm/cpu.c | 3 +-- target/cris/cpu.c | 3 +-- target/i386/cpu.c | 3 +-- target/lm32/cpu.c | 3 +-- target/m68k/cpu.c | 3 +-- target/microblaze/cpu.c | 3 +-- target/mips/cpu.c | 3 +-- target/moxie/cpu.c | 3 +-- target/nios2/cpu.c | 3 +-- target/openrisc/cpu.c | 3 +-- target/ppc/translate_init.inc.c | 3 +-- target/riscv/cpu.c | 3 +-- target/s390x/cpu.c | 3 +-- target/sh4/cpu.c | 3 +-- target/sparc/cpu.c | 3 +-- target/tilegx/cpu.c | 3 +-- target/tricore/cpu.c | 3 +-- target/xtensa/cpu.c | 3 +-- 18 files changed, 18 insertions(+), 36 deletions(-) (limited to 'target') diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d62fd5fdc6..411faaac57 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2707,8 +2707,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) &acc->parent_realize); dc->props = arm_cpu_properties; - acc->parent_reset = cc->reset; - cc->reset = arm_cpu_reset; + cpu_class_set_parent_reset(cc, arm_cpu_reset, &acc->parent_reset); cc->class_by_name = arm_cpu_class_by_name; cc->has_work = arm_cpu_has_work; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 6a857f548d..17c6712e29 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -264,8 +264,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, cris_cpu_realizefn, &ccc->parent_realize); - ccc->parent_reset = cc->reset; - cc->reset = cris_cpu_reset; + cpu_class_set_parent_reset(cc, cris_cpu_reset, &ccc->parent_reset); cc->class_by_name = cris_cpu_class_by_name; cc->has_work = cris_cpu_has_work; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 41f28cebf9..78bdb7ccca 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7149,8 +7149,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) &xcc->parent_unrealize); dc->props = x86_cpu_properties; - xcc->parent_reset = cc->reset; - cc->reset = x86_cpu_reset; + cpu_class_set_parent_reset(cc, x86_cpu_reset, &xcc->parent_reset); cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; cc->class_by_name = x86_cpu_class_by_name; diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index b35537de62..687bf35e65 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -218,8 +218,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, lm32_cpu_realizefn, &lcc->parent_realize); - lcc->parent_reset = cc->reset; - cc->reset = lm32_cpu_reset; + cpu_class_set_parent_reset(cc, lm32_cpu_reset, &lcc->parent_reset); cc->class_by_name = lm32_cpu_class_by_name; cc->has_work = lm32_cpu_has_work; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index f276335faf..f0653cda2f 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -273,8 +273,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data) device_class_set_parent_realize(dc, m68k_cpu_realizefn, &mcc->parent_realize); - mcc->parent_reset = cc->reset; - cc->reset = m68k_cpu_reset; + cpu_class_set_parent_reset(cc, m68k_cpu_reset, &mcc->parent_reset); cc->class_by_name = m68k_cpu_class_by_name; cc->has_work = m68k_cpu_has_work; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 9cfd7445e7..71d88f603b 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -292,8 +292,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, mb_cpu_realizefn, &mcc->parent_realize); - mcc->parent_reset = cc->reset; - cc->reset = mb_cpu_reset; + cpu_class_set_parent_reset(cc, mb_cpu_reset, &mcc->parent_reset); cc->class_by_name = mb_cpu_class_by_name; cc->has_work = mb_cpu_has_work; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index bbcf7ca463..6cd6b9650b 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -189,8 +189,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) device_class_set_parent_realize(dc, mips_cpu_realizefn, &mcc->parent_realize); - mcc->parent_reset = cc->reset; - cc->reset = mips_cpu_reset; + cpu_class_set_parent_reset(cc, mips_cpu_reset, &mcc->parent_reset); cc->class_by_name = mips_cpu_class_by_name; cc->has_work = mips_cpu_has_work; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 48996d0554..cf47bc709b 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -101,8 +101,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, moxie_cpu_realizefn, &mcc->parent_realize); - mcc->parent_reset = cc->reset; - cc->reset = moxie_cpu_reset; + cpu_class_set_parent_reset(cc, moxie_cpu_reset, &mcc->parent_reset); cc->class_by_name = moxie_cpu_class_by_name; diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index ca9c7a6df5..bbdbc0c6fb 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -188,8 +188,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, nios2_cpu_realizefn, &ncc->parent_realize); dc->props = nios2_properties; - ncc->parent_reset = cc->reset; - cc->reset = nios2_cpu_reset; + cpu_class_set_parent_reset(cc, nios2_cpu_reset, &ncc->parent_reset); cc->class_by_name = nios2_cpu_class_by_name; cc->has_work = nios2_cpu_has_work; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 506aec6bfb..5cd04dafab 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -150,8 +150,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, openrisc_cpu_realizefn, &occ->parent_realize); - occ->parent_reset = cc->reset; - cc->reset = openrisc_cpu_reset; + cpu_class_set_parent_reset(cc, openrisc_cpu_reset, &occ->parent_reset); cc->class_by_name = openrisc_cpu_class_by_name; cc->has_work = openrisc_cpu_has_work; diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index d33d65dff7..5ffd07c36a 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -10873,8 +10873,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always; dc->props = ppc_cpu_properties; - pcc->parent_reset = cc->reset; - cc->reset = ppc_cpu_reset; + cpu_class_set_parent_reset(cc, ppc_cpu_reset, &pcc->parent_reset); cc->class_by_name = ppc_cpu_class_by_name; pcc->parent_parse_features = cc->parse_features; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d37861a430..d6f1872728 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -462,8 +462,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) device_class_set_parent_realize(dc, riscv_cpu_realize, &mcc->parent_realize); - mcc->parent_reset = cc->reset; - cc->reset = riscv_cpu_reset; + cpu_class_set_parent_reset(cc, riscv_cpu_reset, &mcc->parent_reset); cc->class_by_name = riscv_cpu_class_by_name; cc->has_work = riscv_cpu_has_work; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 625daeedd1..ca487f5fdd 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -456,12 +456,11 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) dc->props = s390x_cpu_properties; dc->user_creatable = true; - scc->parent_reset = cc->reset; + cpu_class_set_parent_reset(cc, s390_cpu_reset_full, &scc->parent_reset); #if !defined(CONFIG_USER_ONLY) scc->load_normal = s390_cpu_load_normal; #endif scc->reset = s390_cpu_reset; - cc->reset = s390_cpu_reset_full; cc->class_by_name = s390_cpu_class_by_name, cc->has_work = s390_cpu_has_work; #ifdef CONFIG_TCG diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index d0a7707991..70c8d8170f 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -214,8 +214,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, superh_cpu_realizefn, &scc->parent_realize); - scc->parent_reset = cc->reset; - cc->reset = superh_cpu_reset; + cpu_class_set_parent_reset(cc, superh_cpu_reset, &scc->parent_reset); cc->class_by_name = superh_cpu_class_by_name; cc->has_work = superh_cpu_has_work; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index bc65929552..9c306e5271 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -859,8 +859,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) &scc->parent_realize); dc->props = sparc_cpu_properties; - scc->parent_reset = cc->reset; - cc->reset = sparc_cpu_reset; + cpu_class_set_parent_reset(cc, sparc_cpu_reset, &scc->parent_reset); cc->class_by_name = sparc_cpu_class_by_name; cc->parse_features = sparc_cpu_parse_features; diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index 2b2a7ccc31..cd422a0467 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -142,8 +142,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, tilegx_cpu_realizefn, &tcc->parent_realize); - tcc->parent_reset = cc->reset; - cc->reset = tilegx_cpu_reset; + cpu_class_set_parent_reset(cc, tilegx_cpu_reset, &tcc->parent_reset); cc->class_by_name = tilegx_cpu_class_by_name; cc->has_work = tilegx_cpu_has_work; diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index df807c1d74..85bc9f03a1 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -153,8 +153,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data) device_class_set_parent_realize(dc, tricore_cpu_realizefn, &mcc->parent_realize); - mcc->parent_reset = cc->reset; - cc->reset = tricore_cpu_reset; + cpu_class_set_parent_reset(cc, tricore_cpu_reset, &mcc->parent_reset); cc->class_by_name = tricore_cpu_class_by_name; cc->has_work = tricore_cpu_has_work; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index c65dcf9dd7..4856aee8ec 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -184,8 +184,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, xtensa_cpu_realizefn, &xcc->parent_realize); - xcc->parent_reset = cc->reset; - cc->reset = xtensa_cpu_reset; + cpu_class_set_parent_reset(cc, xtensa_cpu_reset, &xcc->parent_reset); cc->class_by_name = xtensa_cpu_class_by_name; cc->has_work = xtensa_cpu_has_work; -- cgit v1.2.3 From 420ae1fc51c99abfd03b1c590f55617edd2a2bed Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 20 Jan 2020 19:21:42 +0100 Subject: target/i386: kvm: initialize feature MSRs very early Some read-only MSRs affect the behavior of ioctls such as KVM_SET_NESTED_STATE. We can initialize them once and for all right after the CPU is realized, since they will never be modified by the guest. Reported-by: Qingua Cheng Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini Message-Id: <1579544504-3616-2-git-send-email-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini --- target/i386/kvm.c | 81 ++++++++++++++++++++++++++++++-------------------- target/i386/kvm_i386.h | 1 + 2 files changed, 49 insertions(+), 33 deletions(-) (limited to 'target') diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 7ee3202634..f6dd6b790e 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -67,6 +67,8 @@ * 255 kvm_msr_entry structs */ #define MSR_BUF_SIZE 4096 +static void kvm_init_msrs(X86CPU *cpu); + const KVMCapabilityInfo kvm_arch_required_capabilities[] = { KVM_CAP_INFO(SET_TSS_ADDR), KVM_CAP_INFO(EXT_CPUID), @@ -1842,6 +1844,8 @@ int kvm_arch_init_vcpu(CPUState *cs) has_msr_tsc_aux = false; } + kvm_init_msrs(cpu); + r = hyperv_init_vcpu(cpu); if (r) { goto fail; @@ -2660,11 +2664,53 @@ static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f) VMCS12_MAX_FIELD_INDEX << 1); } +static int kvm_buf_set_msrs(X86CPU *cpu) +{ + int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf); + if (ret < 0) { + return ret; + } + + if (ret < cpu->kvm_msr_buf->nmsrs) { + struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret]; + error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64, + (uint32_t)e->index, (uint64_t)e->data); + } + + assert(ret == cpu->kvm_msr_buf->nmsrs); + return 0; +} + +static void kvm_init_msrs(X86CPU *cpu) +{ + CPUX86State *env = &cpu->env; + + kvm_msr_buf_reset(cpu); + if (has_msr_arch_capabs) { + kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES, + env->features[FEAT_ARCH_CAPABILITIES]); + } + + if (has_msr_core_capabs) { + kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY, + env->features[FEAT_CORE_CAPABILITY]); + } + + /* + * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but + * all kernels with MSR features should have them. + */ + if (kvm_feature_msrs && cpu_has_vmx(env)) { + kvm_msr_entry_add_vmx(cpu, env->features); + } + + assert(kvm_buf_set_msrs(cpu) == 0); +} + static int kvm_put_msrs(X86CPU *cpu, int level) { CPUX86State *env = &cpu->env; int i; - int ret; kvm_msr_buf_reset(cpu); @@ -2722,17 +2768,6 @@ static int kvm_put_msrs(X86CPU *cpu, int level) } #endif - /* If host supports feature MSR, write down. */ - if (has_msr_arch_capabs) { - kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES, - env->features[FEAT_ARCH_CAPABILITIES]); - } - - if (has_msr_core_capabs) { - kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY, - env->features[FEAT_CORE_CAPABILITY]); - } - /* * The following MSRs have side effects on the guest or are too heavy * for normal writeback. Limit them to reset or full state updates. @@ -2910,14 +2945,6 @@ static int kvm_put_msrs(X86CPU *cpu, int level) /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see * kvm_put_msr_feature_control. */ - - /* - * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but - * all kernels with MSR features should have them. - */ - if (kvm_feature_msrs && cpu_has_vmx(env)) { - kvm_msr_entry_add_vmx(cpu, env->features); - } } if (env->mcg_cap) { @@ -2933,19 +2960,7 @@ static int kvm_put_msrs(X86CPU *cpu, int level) } } - ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf); - if (ret < 0) { - return ret; - } - - if (ret < cpu->kvm_msr_buf->nmsrs) { - struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret]; - error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64, - (uint32_t)e->index, (uint64_t)e->data); - } - - assert(ret == cpu->kvm_msr_buf->nmsrs); - return 0; + return kvm_buf_set_msrs(cpu); } diff --git a/target/i386/kvm_i386.h b/target/i386/kvm_i386.h index 7d0242f5fb..00bde7acaf 100644 --- a/target/i386/kvm_i386.h +++ b/target/i386/kvm_i386.h @@ -46,4 +46,5 @@ bool kvm_enable_x2apic(void); bool kvm_has_x2apic_api(void); bool kvm_hv_vpindex_settable(void); + #endif -- cgit v1.2.3 From 4e45aff398cd1542c2a384a2a3b8600f23337d86 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 20 Jan 2020 19:21:43 +0100 Subject: target/i386: add a ucode-rev property Add the property and plumb it in TCG and HVF (the latter of which tried to support returning a constant value but used the wrong MSR). Signed-off-by: Paolo Bonzini Message-Id: <1579544504-3616-3-git-send-email-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 10 ++++++++++ target/i386/cpu.h | 3 +++ target/i386/hvf/x86_emu.c | 4 +--- target/i386/misc_helper.c | 4 ++++ 4 files changed, 18 insertions(+), 3 deletions(-) (limited to 'target') diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 78bdb7ccca..790254ead6 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6418,6 +6418,15 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) } } + if (cpu->ucode_rev == 0) { + /* The default is the same as KVM's. */ + if (IS_AMD_CPU(env)) { + cpu->ucode_rev = 0x01000065; + } else { + cpu->ucode_rev = 0x100000000ULL; + } + } + /* mwait extended info: needed for Core compatibility */ /* We always wake on interrupt even if host does not have the capability */ cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; @@ -7100,6 +7109,7 @@ static Property x86_cpu_properties[] = { DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), + DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id), DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e6de38ae02..576f309bbf 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -348,6 +348,7 @@ typedef enum X86Seg { #define MSR_IA32_SPEC_CTRL 0x48 #define MSR_VIRT_SSBD 0xc001011f #define MSR_IA32_PRED_CMD 0x49 +#define MSR_IA32_UCODE_REV 0x8b #define MSR_IA32_CORE_CAPABILITY 0xcf #define MSR_IA32_ARCH_CAPABILITIES 0x10a @@ -1627,6 +1628,8 @@ struct X86CPU { CPUNegativeOffsetState neg; CPUX86State env; + uint64_t ucode_rev; + uint32_t hyperv_spinlock_attempts; char *hyperv_vendor_id; bool hyperv_synic_kvm_only; diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index 3df767209d..92ab815f5d 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -664,8 +664,6 @@ static void exec_lods(struct CPUX86State *env, struct x86_decode *decode) RIP(env) += decode->len; } -#define MSR_IA32_UCODE_REV 0x00000017 - void simulate_rdmsr(struct CPUState *cpu) { X86CPU *x86_cpu = X86_CPU(cpu); @@ -681,7 +679,7 @@ void simulate_rdmsr(struct CPUState *cpu) val = cpu_get_apic_base(X86_CPU(cpu)->apic_state); break; case MSR_IA32_UCODE_REV: - val = (0x100000000ULL << 32) | 0x100000000ULL; + val = x86_cpu->ucode_rev; break; case MSR_EFER: val = rvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER); diff --git a/target/i386/misc_helper.c b/target/i386/misc_helper.c index 3eff6885f8..aed16fe3f0 100644 --- a/target/i386/misc_helper.c +++ b/target/i386/misc_helper.c @@ -229,6 +229,7 @@ void helper_rdmsr(CPUX86State *env) #else void helper_wrmsr(CPUX86State *env) { + X86CPU *x86_cpu = env_archcpu(env); uint64_t val; cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1, GETPC()); @@ -371,6 +372,9 @@ void helper_wrmsr(CPUX86State *env) env->msr_bndcfgs = val; cpu_sync_bndcs_hflags(env); break; + case MSR_IA32_UCODE_REV: + val = x86_cpu->ucode_rev; + break; default: if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL && (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL + -- cgit v1.2.3 From 32c87d70ff55b96741f08c35108935cac6f40fe4 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 20 Jan 2020 19:21:44 +0100 Subject: target/i386: kvm: initialize microcode revision from KVM KVM can return the host microcode revision as a feature MSR. Use it as the default value for -cpu host. Signed-off-by: Paolo Bonzini Message-Id: <1579544504-3616-4-git-send-email-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 4 ++++ target/i386/kvm.c | 5 +++++ 2 files changed, 9 insertions(+) (limited to 'target') diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 790254ead6..ffe5de0f82 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6416,6 +6416,10 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) &cpu->mwait.ecx, &cpu->mwait.edx); env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR; } + if (kvm_enabled() && cpu->ucode_rev == 0) { + cpu->ucode_rev = kvm_arch_get_supported_msr_feature(kvm_state, + MSR_IA32_UCODE_REV); + } } if (cpu->ucode_rev == 0) { diff --git a/target/i386/kvm.c b/target/i386/kvm.c index f6dd6b790e..1b67090c5c 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -2696,6 +2696,11 @@ static void kvm_init_msrs(X86CPU *cpu) env->features[FEAT_CORE_CAPABILITY]); } + if (kvm_arch_get_supported_msr_feature(kvm_state, + MSR_IA32_UCODE_REV)) { + kvm_msr_entry_add(cpu, MSR_IA32_UCODE_REV, cpu->ucode_rev); + } + /* * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but * all kernels with MSR features should have them. -- cgit v1.2.3 From d70c996df23f01ee02a661cf085515fc7dac2c5d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 21 Jan 2020 12:03:43 +0100 Subject: target/arm/kvm: Use CPUState::kvm_state in kvm_arm_pmu_supported() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit KVMState is already accessible via CPUState::kvm_state, use it. Reviewed-by: Alistair Francis Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20200121110349.25842-5-philmd@redhat.com> Signed-off-by: Paolo Bonzini --- target/arm/kvm.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'target') diff --git a/target/arm/kvm.c b/target/arm/kvm.c index b87b59a02a..8d82889150 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -181,9 +181,7 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) bool kvm_arm_pmu_supported(CPUState *cpu) { - KVMState *s = KVM_STATE(current_machine->accelerator); - - return kvm_check_extension(s, KVM_CAP_ARM_PMU_V3); + return kvm_check_extension(cpu->kvm_state, KVM_CAP_ARM_PMU_V3); } int kvm_arm_get_max_vm_ipa_size(MachineState *ms) -- cgit v1.2.3 From 4f7f589381d5f75fe5ce9af68bd5a83237c93e3a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 21 Jan 2020 12:03:48 +0100 Subject: accel: Replace current_machine->accelerator by current_accel() wrapper MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We actually want to access the accelerator, not the machine, so use the current_accel() wrapper instead. Suggested-by: Paolo Bonzini Reviewed-by: Alistair Francis Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20200121110349.25842-10-philmd@redhat.com> Signed-off-by: Paolo Bonzini --- target/arm/kvm64.c | 5 ++--- target/i386/kvm.c | 2 +- target/ppc/kvm.c | 4 ++-- 3 files changed, 5 insertions(+), 6 deletions(-) (limited to 'target') diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 876184b8fe..e3c580e749 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -26,7 +26,6 @@ #include "sysemu/kvm.h" #include "sysemu/kvm_int.h" #include "kvm_arm.h" -#include "hw/boards.h" #include "internals.h" static bool have_guest_debug; @@ -613,14 +612,14 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) bool kvm_arm_aarch32_supported(CPUState *cpu) { - KVMState *s = KVM_STATE(current_machine->accelerator); + KVMState *s = KVM_STATE(current_accel()); return kvm_check_extension(s, KVM_CAP_ARM_EL1_32BIT); } bool kvm_arm_sve_supported(CPUState *cpu) { - KVMState *s = KVM_STATE(current_machine->accelerator); + KVMState *s = KVM_STATE(current_accel()); return kvm_check_extension(s, KVM_CAP_ARM_SVE); } diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 1b67090c5c..6ef291d580 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -149,7 +149,7 @@ bool kvm_allows_irq0_override(void) static bool kvm_x2apic_api_set_flags(uint64_t flags) { - KVMState *s = KVM_STATE(current_machine->accelerator); + KVMState *s = KVM_STATE(current_accel()); return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags); } diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index b5799e62b4..06fd0cc162 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -258,7 +258,7 @@ static void kvm_get_smmu_info(struct kvm_ppc_smmu_info *info, Error **errp) struct ppc_radix_page_info *kvm_get_radix_page_info(void) { - KVMState *s = KVM_STATE(current_machine->accelerator); + KVMState *s = KVM_STATE(current_accel()); struct ppc_radix_page_info *radix_page_info; struct kvm_ppc_rmmu_info rmmu_info; int i; @@ -2907,7 +2907,7 @@ void kvmppc_svm_off(Error **errp) return; } - rc = kvm_vm_ioctl(KVM_STATE(current_machine->accelerator), KVM_PPC_SVM_OFF); + rc = kvm_vm_ioctl(KVM_STATE(current_accel()), KVM_PPC_SVM_OFF); if (rc && rc != -ENOTTY) { error_setg_errno(errp, -rc, "KVM_PPC_SVM_OFF ioctl failed"); } -- cgit v1.2.3 From 94d912d1928cabbad20fd6abab0b679682c75058 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= Date: Fri, 10 Jan 2020 19:30:16 +0400 Subject: qdev: remove extraneous error MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All callers use error_abort, and even the function itself calls with error_abort. Signed-off-by: Marc-André Lureau Message-Id: <20200110153039.1379601-4-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini --- target/arm/cpu.c | 36 ++++++++++++------------------------ 1 file changed, 12 insertions(+), 24 deletions(-) (limited to 'target') diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 411faaac57..d161da83eb 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1104,26 +1104,22 @@ void arm_cpu_post_init(Object *obj) if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { - qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property, - &error_abort); + qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property); } if (!arm_feature(&cpu->env, ARM_FEATURE_M)) { - qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property, - &error_abort); + qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); } if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property, - &error_abort); + qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property); } if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { /* Add the has_el3 state CPU property only if EL3 is allowed. This will * prevent "has_el3" from existing on CPUs which cannot support EL3. */ - qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property, - &error_abort); + qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); #ifndef CONFIG_USER_ONLY object_property_add_link(obj, "secure-memory", @@ -1136,8 +1132,7 @@ void arm_cpu_post_init(Object *obj) } if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { - qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property, - &error_abort); + qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); } if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { @@ -1154,32 +1149,27 @@ void arm_cpu_post_init(Object *obj) if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { cpu->has_vfp = true; if (!kvm_enabled()) { - qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property, - &error_abort); + qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property); } } if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { cpu->has_neon = true; if (!kvm_enabled()) { - qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property, - &error_abort); + qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property); } } if (arm_feature(&cpu->env, ARM_FEATURE_M) && arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) { - qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property, - &error_abort); + qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property); } if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) { - qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property, - &error_abort); + qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property); if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { qdev_property_add_static(DEVICE(obj), - &arm_cpu_pmsav7_dregion_property, - &error_abort); + &arm_cpu_pmsav7_dregion_property); } } @@ -1198,12 +1188,10 @@ void arm_cpu_post_init(Object *obj) NULL, NULL, &error_abort); } - qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property, - &error_abort); + qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property); if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) { - qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property, - &error_abort); + qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); } } -- cgit v1.2.3 From 4f67d30b5e74e060b8dbe10528829b47345cd6e8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= Date: Fri, 10 Jan 2020 19:30:32 +0400 Subject: qdev: set properties with device_class_set_props() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The following patch will need to handle properties registration during class_init time. Let's use a device_class_set_props() setter. spatch --macro-file scripts/cocci-macro-file.h --sp-file ./scripts/coccinelle/qdev-set-props.cocci --keep-comments --in-place --dir . @@ typedef DeviceClass; DeviceClass *d; expression val; @@ - d->props = val + device_class_set_props(d, val) Signed-off-by: Marc-André Lureau Message-Id: <20200110153039.1379601-20-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini --- target/arm/cpu.c | 2 +- target/i386/cpu.c | 4 ++-- target/microblaze/cpu.c | 2 +- target/nios2/cpu.c | 2 +- target/ppc/translate_init.inc.c | 10 +++++----- target/riscv/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sparc/cpu.c | 2 +- 8 files changed, 13 insertions(+), 13 deletions(-) (limited to 'target') diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d161da83eb..17cefaa43d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2693,8 +2693,8 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, arm_cpu_realizefn, &acc->parent_realize); - dc->props = arm_cpu_properties; + device_class_set_props(dc, arm_cpu_properties); cpu_class_set_parent_reset(cc, arm_cpu_reset, &acc->parent_reset); cc->class_by_name = arm_cpu_class_by_name; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ffe5de0f82..5fa6acc34f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4144,7 +4144,7 @@ static void max_x86_cpu_class_init(ObjectClass *oc, void *data) xcc->model_description = "Enables all features supported by the accelerator in the current host"; - dc->props = max_x86_cpu_properties; + device_class_set_props(dc, max_x86_cpu_properties); } static void max_x86_cpu_initfn(Object *obj) @@ -7161,7 +7161,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) &xcc->parent_realize); device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, &xcc->parent_unrealize); - dc->props = x86_cpu_properties; + device_class_set_props(dc, x86_cpu_properties); cpu_class_set_parent_reset(cc, x86_cpu_reset, &xcc->parent_reset); cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 71d88f603b..8c90110e52 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -308,7 +308,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) cc->get_phys_page_debug = mb_cpu_get_phys_page_debug; #endif dc->vmsd = &vmstate_mb_cpu; - dc->props = mb_properties; + device_class_set_props(dc, mb_properties); cc->gdb_num_core_regs = 32 + 5; cc->disas_set_info = mb_disas_set_info; diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index bbdbc0c6fb..1c0c855a6f 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -187,7 +187,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, nios2_cpu_realizefn, &ncc->parent_realize); - dc->props = nios2_properties; + device_class_set_props(dc, nios2_properties); cpu_class_set_parent_reset(cc, nios2_cpu_reset, &ncc->parent_reset); cc->class_by_name = nios2_cpu_class_by_name; diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c index 5ffd07c36a..2d3efad233 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -8599,7 +8599,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) dc->fw_name = "PowerPC,POWER7"; dc->desc = "POWER7"; - dc->props = powerpc_servercpu_properties; + device_class_set_props(dc, powerpc_servercpu_properties); pcc->pvr_match = ppc_pvr_match_power7; pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; @@ -8764,7 +8764,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) dc->fw_name = "PowerPC,POWER8"; dc->desc = "POWER8"; - dc->props = powerpc_servercpu_properties; + device_class_set_props(dc, powerpc_servercpu_properties); pcc->pvr_match = ppc_pvr_match_power8; pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; @@ -8976,7 +8976,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) dc->fw_name = "PowerPC,POWER9"; dc->desc = "POWER9"; - dc->props = powerpc_servercpu_properties; + device_class_set_props(dc, powerpc_servercpu_properties); pcc->pvr_match = ppc_pvr_match_power9; pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | @@ -9186,7 +9186,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) dc->fw_name = "PowerPC,POWER10"; dc->desc = "POWER10"; - dc->props = powerpc_servercpu_properties; + device_class_set_props(dc, powerpc_servercpu_properties); pcc->pvr_match = ppc_pvr_match_power10; pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | PCR_COMPAT_3_00; @@ -10871,7 +10871,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) &pcc->parent_unrealize); pcc->pvr_match = ppc_pvr_match_default; pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always; - dc->props = ppc_cpu_properties; + device_class_set_props(dc, ppc_cpu_properties); cpu_class_set_parent_reset(cc, ppc_cpu_reset, &pcc->parent_reset); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d6f1872728..8c86ebc109 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -492,7 +492,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) #endif /* For now, mark unmigratable: */ cc->vmsd = &vmstate_riscv_cpu; - dc->props = riscv_cpu_properties; + device_class_set_props(dc, riscv_cpu_properties); } char *riscv_isa_string(RISCVCPU *cpu) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index ca487f5fdd..cf84d307c6 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -453,7 +453,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, s390_cpu_realizefn, &scc->parent_realize); - dc->props = s390x_cpu_properties; + device_class_set_props(dc, s390x_cpu_properties); dc->user_creatable = true; cpu_class_set_parent_reset(cc, s390_cpu_reset_full, &scc->parent_reset); diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 9c306e5271..eeaecbd8d6 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -857,7 +857,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, sparc_cpu_realizefn, &scc->parent_realize); - dc->props = sparc_cpu_properties; + device_class_set_props(dc, sparc_cpu_properties); cpu_class_set_parent_reset(cc, sparc_cpu_reset, &scc->parent_reset); -- cgit v1.2.3 From 673b0add9ea7f432f34c1c99eaa7c567012fc838 Mon Sep 17 00:00:00 2001 From: Kashyap Chamarthy Date: Thu, 23 Jan 2020 10:01:15 +0100 Subject: target/i386: Add the 'model-id' for Skylake -v3 CPU models This fixes a confusion in the help output. (Although, if you squint long enough at the '-cpu help' output, you _do_ notice that "Skylake-Client-noTSX-IBRS" is an alias of "Skylake-Client-v3"; similarly for Skylake-Server-v3.) Without this patch: $ qemu-system-x86 -cpu help ... x86 Skylake-Client-v1 Intel Core Processor (Skylake) x86 Skylake-Client-v2 Intel Core Processor (Skylake, IBRS) x86 Skylake-Client-v3 Intel Core Processor (Skylake, IBRS) ... x86 Skylake-Server-v1 Intel Xeon Processor (Skylake) x86 Skylake-Server-v2 Intel Xeon Processor (Skylake, IBRS) x86 Skylake-Server-v3 Intel Xeon Processor (Skylake, IBRS) ... With this patch: $ ./qemu-system-x86 -cpu help ... x86 Skylake-Client-v1 Intel Core Processor (Skylake) x86 Skylake-Client-v2 Intel Core Processor (Skylake, IBRS) x86 Skylake-Client-v3 Intel Core Processor (Skylake, IBRS, no TSX) ... x86 Skylake-Server-v1 Intel Xeon Processor (Skylake) x86 Skylake-Server-v2 Intel Xeon Processor (Skylake, IBRS) x86 Skylake-Server-v3 Intel Xeon Processor (Skylake, IBRS, no TSX) ... Signed-off-by: Kashyap Chamarthy Message-Id: <20200123090116.14409-1-kchamart@redhat.com> Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'target') diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5fa6acc34f..32efa46852 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2905,6 +2905,8 @@ static X86CPUDefinition builtin_x86_defs[] = { .props = (PropValue[]) { { "hle", "off" }, { "rtm", "off" }, + { "model-id", + "Intel Core Processor (Skylake, IBRS, no TSX)" }, { /* end of list */ } } }, @@ -3028,6 +3030,8 @@ static X86CPUDefinition builtin_x86_defs[] = { .props = (PropValue[]) { { "hle", "off" }, { "rtm", "off" }, + { "model-id", + "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, { /* end of list */ } } }, -- cgit v1.2.3