From fb00aa61267c8b9c57a2d1a1fa1e336d02e3bcd1 Mon Sep 17 00:00:00 2001 From: Maksim Davydov Date: Thu, 25 May 2023 00:37:48 +0300 Subject: target/i386: EPYC-Rome model without XSAVES Based on the kernel commit "b0563468ee x86/CPU/AMD: Disable XSAVES on AMD family 0x17", host system with EPYC-Rome can clear XSAVES capability bit. In another words, EPYC-Rome host without XSAVES can occur. Thus, we need an EPYC-Rome cpu model (without this feature) that matches the solution of fixing this erratum Signed-off-by: Maksim Davydov Message-Id: <20230524213748.8918-1-davydov-max@yandex-team.ru> Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'target') diff --git a/target/i386/cpu.c b/target/i386/cpu.c index a61cd6d99d..1242bd541a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4466,6 +4466,16 @@ static const X86CPUDefinition builtin_x86_defs[] = { }, .cache_info = &epyc_rome_v3_cache_info }, + { + .version = 4, + .props = (PropValue[]) { + /* Erratum 1386 */ + { "model-id", + "AMD EPYC-Rome-v4 Processor (no XSAVES)" }, + { "xsaves", "off" }, + { /* end of list */ } + }, + }, { /* end of list */ } } }, -- cgit v1.2.3