From 68b981aa76079216f5765a6aecaf8728f27d3696 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 12 Oct 2020 11:57:52 +0200 Subject: target/mips/cpu: Calculate the CP0 timer period using the CPU frequency MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The CP0 timer period is a function of the CPU frequency. Start using the default values, which will be replaced by properties in the next commits. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Jiaxun Yang Message-Id: <20201012095804.3335117-10-f4bug@amsat.org> --- target/mips/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'target') diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 84b727fefa..46188139b7 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -144,13 +144,13 @@ static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) */ #define CPU_FREQ_HZ_DEFAULT 200000000 #define CP0_COUNT_RATE_DEFAULT 2 -#define TIMER_PERIOD_DEFAULT 10 /* 1 / (CPU_FREQ_HZ / CP0_COUNT_RATE) */ static void mips_cp0_period_set(MIPSCPU *cpu) { CPUMIPSState *env = &cpu->env; - env->cp0_count_ns = TIMER_PERIOD_DEFAULT; + env->cp0_count_ns = muldiv64(NANOSECONDS_PER_SECOND, CP0_COUNT_RATE_DEFAULT, + CPU_FREQ_HZ_DEFAULT); } static void mips_cpu_realizefn(DeviceState *dev, Error **errp) -- cgit v1.2.3