From 0e235827de65b8a0a5fa403ad9ed15d04f8b1a4f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Wed, 13 Oct 2021 23:42:37 +0200 Subject: target/mips: Fix DEXTRV_S.H DSP opcode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit While for the DEXTR_S.H opcode: "The shift argument is provided in the instruction." For the DEXTRV_S.H opcode we have: "The five least-significant bits of register rs provide the shift argument, interpreted as a five-bit unsigned integer; the remaining bits in rs are ignored." While 't1' contains the 'rs' register content (the shift value for DEXTR_S.H), we need to load the value of 'rs' for DEXTRV_S.H. We can directly use the v1_t TCG register which already contains this shift value. Fixes: b53371ed5d4 ("target-mips: Add ASE DSP accumulator instructions") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20211013215652.1764551-1-f4bug@amsat.org> --- target/mips/tcg/translate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'target') diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 5fdeb67e82..519b00121f 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -13796,8 +13796,7 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2, break; case OPC_DEXTRV_S_H: tcg_gen_movi_tl(t0, v2); - tcg_gen_movi_tl(t1, v1); - gen_helper_dextr_s_h(cpu_gpr[ret], t0, t1, cpu_env); + gen_helper_dextr_s_h(cpu_gpr[ret], t0, v1_t, cpu_env); break; case OPC_DEXTRV_L: tcg_gen_movi_tl(t0, v2); -- cgit v1.2.3