From 5b9b27639e4af3e957da1959ad51f94e53c2e6f1 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 20 Feb 2017 10:41:45 -0800 Subject: target/xtensa: drop DisasContext::litbase It doesn't help much, always-set bit 0 of the LITBASE SR is easy to compensate with decrement of the l32r immediate argument. Signed-off-by: Max Filippov --- target/xtensa/translate.c | 27 +++++---------------------- 1 file changed, 5 insertions(+), 22 deletions(-) (limited to 'target/xtensa') diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index cf204fcb60..27078e9f5b 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -59,7 +59,6 @@ typedef struct DisasContext { int ring; uint32_t lbeg; uint32_t lend; - TCGv_i32 litbase; int is_jmp; int singlestep_enabled; @@ -261,21 +260,6 @@ static inline bool option_enabled(DisasContext *dc, int opt) return xtensa_option_enabled(dc->config, opt); } -static void init_litbase(DisasContext *dc) -{ - if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { - dc->litbase = tcg_temp_local_new_i32(); - tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000); - } -} - -static void reset_litbase(DisasContext *dc) -{ - if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { - tcg_temp_free(dc->litbase); - } -} - static void init_sar_tracker(DisasContext *dc) { dc->sar_5bit = false; @@ -1089,7 +1073,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) dc.slotbuf = xtensa_insnbuf_alloc(dc.config->isa); } - init_litbase(&dc); init_sar_tracker(&dc); if (dc.icount) { dc.next_icount = tcg_temp_local_new_i32(); @@ -1164,7 +1147,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) dc.pc + xtensa_insn_len(env, &dc) <= next_page_start && !tcg_op_buf_full()); done: - reset_litbase(&dc); reset_sar_tracker(&dc); if (dc.icount) { tcg_temp_free(dc.next_icount); @@ -1667,12 +1649,13 @@ static void translate_l32r(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { if (gen_window_check1(dc, arg[0])) { - TCGv_i32 tmp = (dc->tb->flags & XTENSA_TBFLAG_LITBASE) ? - tcg_const_i32(dc->raw_arg[1] - 1) : - tcg_const_i32(arg[1]); + TCGv_i32 tmp; if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { - tcg_gen_add_i32(tmp, tmp, dc->litbase); + tmp = tcg_const_i32(dc->raw_arg[1] - 1); + tcg_gen_add_i32(tmp, cpu_SR[LITBASE], tmp); + } else { + tmp = tcg_const_i32(arg[1]); } tcg_gen_qemu_ld32u(cpu_R[arg[0]], tmp, dc->cring); tcg_temp_free(tmp); -- cgit v1.2.3