From 8f75983db8d67bce42332db7b38c62e2d45a5c7f Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Thu, 6 Oct 2016 16:46:36 +0200 Subject: target-tricore: Added FTOUZ instruction Converts a 32-bit floating point number to an unsigned int. The result is rounded towards zero. Signed-off-by: Bastian Koppelmann Reviewed-by: Richard Henderson --- target/tricore/translate.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'target/tricore/translate.c') diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 36f734a662..eb6fdc3ca4 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -6698,6 +6698,9 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) case OPC2_32_RR_ITOF: gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); break; + case OPC2_32_RR_FTOUZ: + gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); + break; default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } -- cgit v1.2.3 From ddd7fead8c8524dc51b9b7c20b1f08a4b34ef653 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Thu, 6 Oct 2016 16:50:53 +0200 Subject: target-tricore: Added MADD.F and MSUB.F instructions Multiplies D[a] and D[b] and adds/subtracts the result to/from D[d]. The result is put in D[c]. All operands are floating-point numbers. Signed-off-by: Bastian Koppelmann Reviewed-by: Richard Henderson --- target/tricore/translate.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'target/tricore/translate.c') diff --git a/target/tricore/translate.c b/target/tricore/translate.c index eb6fdc3ca4..a8234dba83 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -7096,6 +7096,14 @@ static void decode_rrr_divide(CPUTriCoreState *env, DisasContext *ctx) case OPC2_32_RRR_SUB_F: gen_helper_fsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]); break; + case OPC2_32_RRR_MADD_F: + gen_helper_fmadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], + cpu_gpr_d[r2], cpu_gpr_d[r3]); + break; + case OPC2_32_RRR_MSUB_F: + gen_helper_fmsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], + cpu_gpr_d[r2], cpu_gpr_d[r3]); + break; default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } -- cgit v1.2.3 From 550929dd4622f8e2b1b5c277f32089d83cb1e595 Mon Sep 17 00:00:00 2001 From: Peer Adelt Date: Tue, 7 Jun 2016 17:49:14 +0200 Subject: target-tricore: Added new MOV instruction variant Puts the content of data register D[a] into E[c][63:32] and the content of data register D[b] into E[c][31:0]. [BK: fix style error] [BK: Allocate temporaries only when needed] Signed-off-by: Peer Adelt Message-Id: <1465314555-11501-4-git-send-email-peer.adelt@c-lab.de> Signed-off-by: Bastian Koppelmann --- target/tricore/translate.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'target/tricore/translate.c') diff --git a/target/tricore/translate.c b/target/tricore/translate.c index a8234dba83..1cdd87e8fb 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -6034,6 +6034,8 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) uint32_t op2; int r3, r2, r1; + TCGv temp; + r3 = MASK_OP_RR_D(ctx->opcode); r2 = MASK_OP_RR_S2(ctx->opcode); r1 = MASK_OP_RR_S1(ctx->opcode); @@ -6224,6 +6226,20 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) case OPC2_32_RR_MOV: tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); break; + case OPC2_32_RR_MOV_64: + if (tricore_feature(env, TRICORE_FEATURE_16)) { + temp = tcg_temp_new(); + + CHECK_REG_PAIR(r3); + tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); + tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); + tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp); + + tcg_temp_free(temp); + } else { + generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); + } + break; case OPC2_32_RR_NE: tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); -- cgit v1.2.3 From dedd8c9c32cf753d1868d347b985c36a0a02af9a Mon Sep 17 00:00:00 2001 From: Peer Adelt Date: Tue, 7 Jun 2016 17:49:15 +0200 Subject: target-tricore: Added new JNE instruction variant If D[15] is != sign_ext(const4) then PC will be set to (PC + zero_ext(disp4 + 16)). [BK: fixed style errors] Signed-off-by: Peer Adelt Message-Id: <1465314555-11501-5-git-send-email-peer.adelt@c-lab.de> Signed-off-by: Bastian Koppelmann --- target/tricore/translate.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'target/tricore/translate.c') diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 1cdd87e8fb..9d1ee66b94 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -3362,9 +3362,17 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, case OPC1_16_SBC_JEQ: gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset); break; + case OPC1_16_SBC_JEQ2: + gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, + offset + 16); + break; case OPC1_16_SBC_JNE: gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset); break; + case OPC1_16_SBC_JNE2: + gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], + constant, offset + 16); + break; /* SBRN-format jumps */ case OPC1_16_SBRN_JZ_T: temp = tcg_temp_new(); @@ -4097,6 +4105,16 @@ static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx) const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); gen_compute_branch(ctx, op1, 0, 0, const16, address); break; + case OPC1_16_SBC_JEQ2: + case OPC1_16_SBC_JNE2: + if (tricore_feature(env, TRICORE_FEATURE_16)) { + address = MASK_OP_SBC_DISP4(ctx->opcode); + const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); + gen_compute_branch(ctx, op1, 0, 0, const16, address); + } else { + generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); + } + break; /* SBRN-format */ case OPC1_16_SBRN_JNZ_T: case OPC1_16_SBRN_JZ_T: -- cgit v1.2.3 From 50788a3fdbade5f8ed1c8296988578133c52c6aa Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Thu, 6 Oct 2016 17:52:04 +0200 Subject: target-tricore: Add updfl instruction Signed-off-by: Bastian Koppelmann Reviewed-by: Richard Henderson --- target/tricore/translate.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'target/tricore/translate.c') diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 9d1ee66b94..54249c1547 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -6735,6 +6735,9 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) case OPC2_32_RR_FTOUZ: gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); break; + case OPC2_32_RR_UPDFL: + gen_helper_updfl(cpu_env, cpu_gpr_d[r1]); + break; default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } -- cgit v1.2.3