From bb03fd841cb33f3a85cedc1f89169fe2649fc258 Mon Sep 17 00:00:00 2001 From: David Hildenbrand Date: Wed, 29 May 2019 21:42:05 +0200 Subject: s390x/tcg: Implement VECTOR FP CONVERT FROM FIXED 64-BIT 1. We'll reuse op_vcdg() for similar instructions later, prepare for that. 2. We'll reuse vop64_2() later for other instructions. We have to mangle the erm (effective rounding mode) and the m4 into the simd_data(), and properly unmangle them again. Make sure to restore the erm before triggering an exception. Reviewed-by: Richard Henderson Signed-off-by: David Hildenbrand --- target/s390x/translate_vx.inc.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'target/s390x/translate_vx.inc.c') diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c index 5571a71e1a..6741b707cc 100644 --- a/target/s390x/translate_vx.inc.c +++ b/target/s390x/translate_vx.inc.c @@ -2639,3 +2639,28 @@ static DisasJumpType op_vfc(DisasContext *s, DisasOps *o) } return DISAS_NEXT; } + +static DisasJumpType op_vcdg(DisasContext *s, DisasOps *o) +{ + const uint8_t fpf = get_field(s->fields, m3); + const uint8_t m4 = get_field(s->fields, m4); + const uint8_t erm = get_field(s->fields, m5); + const bool se = extract32(m4, 3, 1); + gen_helper_gvec_2_ptr *fn; + + if (fpf != FPF_LONG || extract32(m4, 0, 2) || erm > 7 || erm == 2) { + gen_program_exception(s, PGM_SPECIFICATION); + return DISAS_NORETURN; + } + + switch (s->fields->op2) { + case 0xc3: + fn = se ? gen_helper_gvec_vcdg64s : gen_helper_gvec_vcdg64; + break; + default: + g_assert_not_reached(); + } + gen_gvec_2_ptr(get_field(s->fields, v1), get_field(s->fields, v2), cpu_env, + deposit32(m4, 4, 4, erm), fn); + return DISAS_NEXT; +} -- cgit v1.2.3