From ad9e5aa2ae8032f19a8293b6b8f4661c06167bf0 Mon Sep 17 00:00:00 2001 From: LIU Zhiwei Date: Wed, 1 Jul 2020 23:24:49 +0800 Subject: target/riscv: add vector extension field in CPURISCVState The 32 vector registers will be viewed as a continuous memory block. It avoids the convension between element index and (regno, offset). Thus elements can be directly accessed by offset from the first vector base address. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis Reviewed-by: Richard Henderson Message-Id: <20200701152549.1218-2-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis --- target/riscv/translate.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'target/riscv/translate.c') diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ce71ca7a92..b269f15920 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -32,7 +32,7 @@ #include "instmap.h" /* global register indices */ -static TCGv cpu_gpr[32], cpu_pc; +static TCGv cpu_gpr[32], cpu_pc, cpu_vl; static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ static TCGv load_res; static TCGv load_val; @@ -887,6 +887,7 @@ void riscv_translate_init(void) } cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); + cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), "load_res"); load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), -- cgit v1.2.3