From 98898b20e9cca462843c22ad952c216ffd57d654 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Wed, 13 Feb 2019 07:54:01 -0800 Subject: target/riscv: Remove manual decoding from gen_load() With decodetree we don't need to convert RISC-V opcodes into to MemOps as the old gen_load() did. Reviewed-by: Richard Henderson Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/translate.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'target/riscv/translate.c') diff --git a/target/riscv/translate.c b/target/riscv/translate.c index a3d5cdbad8..99d6d3b4ae 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -531,7 +531,8 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) ctx->base.is_jmp = DISAS_NORETURN; } -static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1, +#ifdef TARGET_RISCV64 +static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1, target_long imm) { TCGv t0 = tcg_temp_new(); @@ -550,6 +551,7 @@ static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1, tcg_temp_free(t0); tcg_temp_free(t1); } +#endif static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2, target_long imm) @@ -723,7 +725,7 @@ static void decode_RV32_64C0(DisasContext *ctx) case 3: #if defined(TARGET_RISCV64) /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/ - gen_load(ctx, OPC_RISC_LD, rd_rs2, rs1s, + gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s, GET_C_LD_IMM(ctx->opcode)); #else /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/ -- cgit v1.2.3