From 6591efb54966cb08bfd7398261caa2fc2184efeb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 23 Jul 2019 14:08:16 +0200 Subject: target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the always-compiled trace events, remove the now unused RISCV_DEBUG_PMP definition. Note pmpaddr_csr_read() could previously do out-of-bound accesses passing addr_index >= MAX_RISCV_PMPS. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/trace-events | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'target/riscv/trace-events') diff --git a/target/riscv/trace-events b/target/riscv/trace-events index 48af0373df..4b6c652ae9 100644 --- a/target/riscv/trace-events +++ b/target/riscv/trace-events @@ -1,2 +1,8 @@ # target/riscv/cpu_helper.c riscv_trap(uint64_t hartid, bool async, uint64_t cause, uint64_t epc, uint64_t tval, const char *desc) "hart:%"PRId64", async:%d, cause:%"PRId64", epc:0x%"PRIx64", tval:0x%"PRIx64", desc=%s" + +# pmp.c +pmpcfg_csr_read(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRIu64 ": read reg%" PRIu32", val: 0x%" PRIx64 +pmpcfg_csr_write(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRIu64 ": write reg%" PRIu32", val: 0x%" PRIx64 +pmpaddr_csr_read(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": read addr%" PRIu32", val: 0x%" PRIx64 +pmpaddr_csr_write(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": write addr%" PRIu32", val: 0x%" PRIx64 -- cgit v1.2.3