From 05e6ca5e156d1d114d1eb878cae9744cb4a539e3 Mon Sep 17 00:00:00 2001 From: Guo Ren Date: Fri, 4 Feb 2022 10:26:54 +0800 Subject: target/riscv: Ignore reserved bits in PTE for RV64 Highest bits of PTE has been used for svpbmt, ref: [1], [2], so we need to ignore them. They cannot be a part of ppn. 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture 4.4 Sv39: Page-Based 39-bit Virtual-Memory System 4.5 Sv48: Page-Based 48-bit Virtual-Memory System 2: https://github.com/riscv/virtual-memory/blob/main/specs/663-Svpbmt-diff.pdf Signed-off-by: Guo Ren Reviewed-by: Liu Zhiwei Reviewed-by: Alistair Francis Cc: Bin Meng Reviewed-by: Alistair Francis Message-Id: <20220204022658.18097-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'target/riscv/cpu_bits.h') diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 068c4d8034..b3489cbc10 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -565,6 +565,9 @@ typedef enum { /* Page table PPN shift amount */ #define PTE_PPN_SHIFT 10 +/* Page table PPN mask */ +#define PTE_PPN_MASK 0x3FFFFFFFFFFC00ULL + /* Leaf page shift amount */ #define PGSHIFT 12 -- cgit v1.2.3