From a2c975e119af289d8611df1d8649685b928cfd71 Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Thu, 4 Nov 2021 09:36:56 -0300 Subject: target/ppc: Implement vclzdm/vctzdm instructions The signature of do_cntzdm is changed to allow reuse as GVecGen3i.fni8. The method is also moved out of #ifdef TARGET_PPC64, as PowerISA doesn't say vclzdm and vctzdm are 64-bit only. Reviewed-by: Richard Henderson Signed-off-by: Luis Pires Signed-off-by: Matheus Ferst Message-Id: <20211104123719.323713-3-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson --- target/ppc/translate/vmx-impl.c.inc | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'target/ppc/translate/vmx-impl.c.inc') diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc index e36c66589c..6da8a9123f 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -1575,6 +1575,38 @@ static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a) return true; } +static bool trans_VCLZDM(DisasContext *ctx, arg_VX *a) +{ + static const GVecGen3i g = { + .fni8 = do_cntzdm, + .vece = MO_64, + }; + + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + REQUIRE_VECTOR(ctx); + + tcg_gen_gvec_3i(avr_full_offset(a->vrt), avr_full_offset(a->vra), + avr_full_offset(a->vrb), 16, 16, false, &g); + + return true; +} + +static bool trans_VCTZDM(DisasContext *ctx, arg_VX *a) +{ + static const GVecGen3i g = { + .fni8 = do_cntzdm, + .vece = MO_64, + }; + + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + REQUIRE_VECTOR(ctx); + + tcg_gen_gvec_3i(avr_full_offset(a->vrt), avr_full_offset(a->vra), + avr_full_offset(a->vrb), 16, 16, true, &g); + + return true; +} + #undef GEN_VR_LDX #undef GEN_VR_STX #undef GEN_VR_LVE -- cgit v1.2.3