From 7aeac354a6925afcec684e985d56e612f9e81b2d Mon Sep 17 00:00:00 2001 From: Daniel Henrique Barboza Date: Fri, 17 Dec 2021 17:57:18 +0100 Subject: target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PM_RUN_INST_CMPL, instructions completed with the run latch set, is the architected PowerISA v3.1 event defined with PMC4SEL = 0xFA. Implement it by checking for the CTRL RUN bit before incrementing the counter. To make this work properly we also need to force a new translation block each time SPR_CTRL is written. A small tweak in pmu_increment_insns() is then needed to only increment this event if the thread has the run latch. Reviewed-by: David Gibson Signed-off-by: Daniel Henrique Barboza Message-Id: <20211201151734.654994-8-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater --- target/ppc/power8-pmu.c | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) (limited to 'target/ppc/power8-pmu.c') diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index e163ba5640..08d1902cd5 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -96,6 +96,15 @@ static PMUEventType pmc_get_event(CPUPPCState *env, int sprn) evt_type = PMU_EVENT_CYCLES; } break; + case 0xFA: + /* + * PMC4SEL = 0xFA is the "instructions completed + * with run latch set" event. + */ + if (sprn == SPR_POWER_PMC4) { + evt_type = PMU_EVENT_INSN_RUN_LATCH; + } + break; case 0xFE: /* * PMC1SEL = 0xFE is the architected PowerISA v3.1 @@ -117,7 +126,8 @@ bool pmu_insn_cnt_enabled(CPUPPCState *env) int sprn; for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC5; sprn++) { - if (pmc_get_event(env, sprn) == PMU_EVENT_INSTRUCTIONS) { + if (pmc_get_event(env, sprn) == PMU_EVENT_INSTRUCTIONS || + pmc_get_event(env, sprn) == PMU_EVENT_INSN_RUN_LATCH) { return true; } } @@ -132,11 +142,22 @@ static bool pmu_increment_insns(CPUPPCState *env, uint32_t num_insns) /* PMC6 never counts instructions */ for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC5; sprn++) { - if (pmc_get_event(env, sprn) != PMU_EVENT_INSTRUCTIONS) { + PMUEventType evt_type = pmc_get_event(env, sprn); + bool insn_event = evt_type == PMU_EVENT_INSTRUCTIONS || + evt_type == PMU_EVENT_INSN_RUN_LATCH; + + if (pmc_is_inactive(env, sprn) || !insn_event) { continue; } - env->spr[sprn] += num_insns; + if (evt_type == PMU_EVENT_INSTRUCTIONS) { + env->spr[sprn] += num_insns; + } + + if (evt_type == PMU_EVENT_INSN_RUN_LATCH && + env->spr[SPR_CTRL] & CTRL_RUN) { + env->spr[sprn] += num_insns; + } if (env->spr[sprn] >= PMC_COUNTER_NEGATIVE_VAL && pmc_has_overflow_enabled(env, sprn)) { -- cgit v1.2.3