From b72e3ff65880f2b894a2692e2b0a14424058a919 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sun, 25 Aug 2019 14:28:37 -0700 Subject: target/openrisc: Make VR and PPC read-only These SPRs are read-only. The writes can simply be ignored, as we already do for other read-only (or missing) registers. There is no reason to mask the value in env->vr. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 3 --- target/openrisc/sys_helper.c | 10 +--------- 2 files changed, 1 insertion(+), 12 deletions(-) (limited to 'target/openrisc') diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 561f0f7fad..755282f95d 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -68,9 +68,6 @@ enum { (reg) |= ((v & 0x1f) << 2);\ } while (0) -/* Version Register */ -#define SPR_VR 0xFFFF003F - /* Interrupt */ #define NR_IRQS 32 diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 1053409a04..d20f48b659 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -39,10 +39,6 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) int idx; switch (spr) { - case TO_SPR(0, 0): /* VR */ - env->vr = rb; - break; - case TO_SPR(0, 11): /* EVBAR */ env->evbar = rb; break; @@ -62,10 +58,6 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) cpu_set_sr(env, rb); break; - case TO_SPR(0, 18): /* PPC */ - env->ppc = rb; - break; - case TO_SPR(0, 32): /* EPCR */ env->epcr = rb; break; @@ -204,7 +196,7 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, switch (spr) { case TO_SPR(0, 0): /* VR */ - return env->vr & SPR_VR; + return env->vr; case TO_SPR(0, 1): /* UPR */ return env->upr; /* TT, DM, IM, UP present */ -- cgit v1.2.3