From c7efab4fc1fe5092136305a2cae67fca03f4f9c5 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sun, 25 Aug 2019 15:02:54 -0700 Subject: target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init These registers are read-only and implementation specific. Initiailize VR for the first time; take the OR1200 values from the verilog source. Note that moving fields within CPUOpenRISCState does not affect migration. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'target/openrisc/cpu.h') diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 755282f95d..18d7445e74 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -260,10 +260,6 @@ typedef struct CPUOpenRISCState { target_ulong sr_cy; /* the SR_CY bit, values 0, 1. */ target_long sr_ov; /* the SR_OV bit (in the sign bit only) */ uint32_t sr; /* Supervisor register, without SR_{F,CY,OV} */ - uint32_t vr; /* Version register */ - uint32_t upr; /* Unit presence register */ - uint32_t dmmucfgr; /* DMMU configure register */ - uint32_t immucfgr; /* IMMU configure register */ uint32_t esr; /* Exception supervisor register */ uint32_t evbar; /* Exception vector base address register */ uint32_t pmr; /* Power Management Register */ @@ -283,7 +279,11 @@ typedef struct CPUOpenRISCState { struct {} end_reset_fields; /* Fields from here on are preserved across CPU reset. */ + uint32_t vr; /* Version register */ + uint32_t upr; /* Unit presence register */ uint32_t cpucfgr; /* CPU configure register */ + uint32_t dmmucfgr; /* DMMU configure register */ + uint32_t immucfgr; /* IMMU configure register */ #ifndef CONFIG_USER_ONLY QEMUTimer *timer; -- cgit v1.2.3