From 36b84f856ed67f5b2ee2e26368f7009f3222ba46 Mon Sep 17 00:00:00 2001 From: Marcin Nowakowski Date: Thu, 16 Feb 2023 06:17:16 +0100 Subject: target/mips: Implement CP0.Config7.WII bit support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some pre-release 6 cores use CP0.Config7.WII bit to indicate that a disabled interrupt should wake up a sleeping CPU. Enable this bit by default for M14K(c) and P5600. There are potentially other cores that support this feature, but I do not have a complete list. Signed-off-by: Marcin Nowakowski Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20230216051717.3911212-4-marcin.nowakowski@fungible.com> Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'target/mips/cpu.c') diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 05caf54999..543da911e3 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -143,11 +143,13 @@ static bool mips_cpu_has_work(CPUState *cs) /* * Prior to MIPS Release 6 it is implementation dependent if non-enabled * interrupts wake-up the CPU, however most of the implementations only - * check for interrupts that can be taken. + * check for interrupts that can be taken. For pre-release 6 CPUs, + * check for CP0 Config7 'Wait IE ignore' bit. */ if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && cpu_mips_hw_interrupts_pending(env)) { if (cpu_mips_hw_interrupts_enabled(env) || + (env->CP0_Config7 & (1 << CP0C7_WII)) || (env->insn_flags & ISA_MIPS_R6)) { has_work = true; } -- cgit v1.2.3