From 14f944063affbcc7bd6df42b060793dbfee8a822 Mon Sep 17 00:00:00 2001 From: Laurent Vivier Date: Mon, 11 Jan 2016 01:33:26 +0100 Subject: target-m68k: add cas/cas2 ops Implement CAS using cmpxchg. Implement CAS2 using helper and either cmpxchg when the 32bit addresses are consecutive, or with parallel_cpus+cpu_loop_exit_atomic() otherwise. Suggested-by: Richard Henderson Signed-off-by: Laurent Vivier Reviewed-by: Richard Henderson --- target/m68k/op_helper.c | 109 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 109 insertions(+) (limited to 'target/m68k/op_helper.c') diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 04246a92b4..e56b815d73 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -360,3 +360,112 @@ void HELPER(divsll)(CPUM68KState *env, int numr, int regr, int32_t den) env->dregs[regr] = rem; env->dregs[numr] = quot; } + +void HELPER(cas2w)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2) +{ + uint32_t Dc1 = extract32(regs, 9, 3); + uint32_t Dc2 = extract32(regs, 6, 3); + uint32_t Du1 = extract32(regs, 3, 3); + uint32_t Du2 = extract32(regs, 0, 3); + int16_t c1 = env->dregs[Dc1]; + int16_t c2 = env->dregs[Dc2]; + int16_t u1 = env->dregs[Du1]; + int16_t u2 = env->dregs[Du2]; + int16_t l1, l2; + uintptr_t ra = GETPC(); + + if (parallel_cpus) { + /* Tell the main loop we need to serialize this insn. */ + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + } else { + /* We're executing in a serial context -- no need to be atomic. */ + l1 = cpu_lduw_data_ra(env, a1, ra); + l2 = cpu_lduw_data_ra(env, a2, ra); + if (l1 == c1 && l2 == c2) { + cpu_stw_data_ra(env, a1, u1, ra); + cpu_stw_data_ra(env, a2, u2, ra); + } + } + + if (c1 != l1) { + env->cc_n = l1; + env->cc_v = c1; + } else { + env->cc_n = l2; + env->cc_v = c2; + } + env->cc_op = CC_OP_CMPW; + env->dregs[Dc1] = deposit32(env->dregs[Dc1], 0, 16, l1); + env->dregs[Dc2] = deposit32(env->dregs[Dc2], 0, 16, l2); +} + +void HELPER(cas2l)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2) +{ + uint32_t Dc1 = extract32(regs, 9, 3); + uint32_t Dc2 = extract32(regs, 6, 3); + uint32_t Du1 = extract32(regs, 3, 3); + uint32_t Du2 = extract32(regs, 0, 3); + uint32_t c1 = env->dregs[Dc1]; + uint32_t c2 = env->dregs[Dc2]; + uint32_t u1 = env->dregs[Du1]; + uint32_t u2 = env->dregs[Du2]; + uint32_t l1, l2; + uintptr_t ra = GETPC(); +#if defined(CONFIG_ATOMIC64) && !defined(CONFIG_USER_ONLY) + int mmu_idx = cpu_mmu_index(env, 0); + TCGMemOpIdx oi; +#endif + + if (parallel_cpus) { + /* We're executing in a parallel context -- must be atomic. */ +#ifdef CONFIG_ATOMIC64 + uint64_t c, u, l; + if ((a1 & 7) == 0 && a2 == a1 + 4) { + c = deposit64(c2, 32, 32, c1); + u = deposit64(u2, 32, 32, u1); +#ifdef CONFIG_USER_ONLY + l = helper_atomic_cmpxchgq_be(env, a1, c, u); +#else + oi = make_memop_idx(MO_BEQ, mmu_idx); + l = helper_atomic_cmpxchgq_be_mmu(env, a1, c, u, oi, ra); +#endif + l1 = l >> 32; + l2 = l; + } else if ((a2 & 7) == 0 && a1 == a2 + 4) { + c = deposit64(c1, 32, 32, c2); + u = deposit64(u1, 32, 32, u2); +#ifdef CONFIG_USER_ONLY + l = helper_atomic_cmpxchgq_be(env, a2, c, u); +#else + oi = make_memop_idx(MO_BEQ, mmu_idx); + l = helper_atomic_cmpxchgq_be_mmu(env, a2, c, u, oi, ra); +#endif + l2 = l >> 32; + l1 = l; + } else +#endif + { + /* Tell the main loop we need to serialize this insn. */ + cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); + } + } else { + /* We're executing in a serial context -- no need to be atomic. */ + l1 = cpu_ldl_data_ra(env, a1, ra); + l2 = cpu_ldl_data_ra(env, a2, ra); + if (l1 == c1 && l2 == c2) { + cpu_stl_data_ra(env, a1, u1, ra); + cpu_stl_data_ra(env, a2, u2, ra); + } + } + + if (c1 != l1) { + env->cc_n = l1; + env->cc_v = c1; + } else { + env->cc_n = l2; + env->cc_v = c2; + } + env->cc_op = CC_OP_CMPL; + env->dregs[Dc1] = l1; + env->dregs[Dc2] = l2; +} -- cgit v1.2.3