From 3966582099b0c94b45a2ea0fd8afb0dcac8ad292 Mon Sep 17 00:00:00 2001 From: Jiajie Chen Date: Tue, 22 Aug 2023 09:13:50 +0200 Subject: target/loongarch: Add LA64 & VA32 to DisasContext Add LA64 and VA32(32-bit Virtual Address) to DisasContext to allow the translator to reject doubleword instructions in LA32 mode for example. Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-ID: <20230822032724.1353391-5-gaosong@loongson.cn> Message-Id: <20230822071405.35386-5-philmd@linaro.org> --- target/loongarch/translate.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'target/loongarch/translate.c') diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index 3146a2d4ac..ac847745df 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -119,6 +119,9 @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase, ctx->vl = LSX_LEN; } + ctx->la64 = is_la64(env); + ctx->va32 = (ctx->base.tb->flags & HW_FLAGS_VA32) != 0; + ctx->zero = tcg_constant_tl(0); } -- cgit v1.2.3 From 34423c01941928974f4854bc23a949789154fee7 Mon Sep 17 00:00:00 2001 From: Jiajie Chen Date: Tue, 22 Aug 2023 09:13:51 +0200 Subject: target/loongarch: Extract make_address_x() helper MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Jiajie Chen Co-authored-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20230822071405.35386-6-philmd@linaro.org> --- target/loongarch/translate.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'target/loongarch/translate.c') diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index ac847745df..a68a979a55 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -208,6 +208,18 @@ static void set_fpr(int reg_num, TCGv val) offsetof(CPULoongArchState, fpr[reg_num].vreg.D(0))); } +static TCGv make_address_x(DisasContext *ctx, TCGv base, TCGv addend) +{ + TCGv temp = NULL; + + if (addend) { + temp = tcg_temp_new(); + tcg_gen_add_tl(temp, base, addend); + base = temp; + } + return base; +} + #include "decode-insns.c.inc" #include "insn_trans/trans_arith.c.inc" #include "insn_trans/trans_shift.c.inc" -- cgit v1.2.3 From c5af6628f4be5d30800233e59ba3842ca19a12e6 Mon Sep 17 00:00:00 2001 From: Jiajie Chen Date: Tue, 22 Aug 2023 09:13:52 +0200 Subject: target/loongarch: Extract make_address_i() helper MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Jiajie Chen Co-authored-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20230822071405.35386-7-philmd@linaro.org> --- target/loongarch/translate.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'target/loongarch/translate.c') diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index a68a979a55..acc54d7587 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -220,6 +220,12 @@ static TCGv make_address_x(DisasContext *ctx, TCGv base, TCGv addend) return base; } +static TCGv make_address_i(DisasContext *ctx, TCGv base, target_long ofs) +{ + TCGv addend = ofs ? tcg_constant_tl(ofs) : NULL; + return make_address_x(ctx, base, addend); +} + #include "decode-insns.c.inc" #include "insn_trans/trans_arith.c.inc" #include "insn_trans/trans_shift.c.inc" -- cgit v1.2.3 From 5a7ce25d0db050b8ddd62dc91c56f4af46e9cf3c Mon Sep 17 00:00:00 2001 From: Jiajie Chen Date: Tue, 22 Aug 2023 09:13:53 +0200 Subject: target/loongarch: Extract make_address_pc() helper MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230822032724.1353391-7-gaosong@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20230822071405.35386-8-philmd@linaro.org> --- target/loongarch/translate.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'target/loongarch/translate.c') diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index acc54d7587..8b26555a27 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -226,6 +226,11 @@ static TCGv make_address_i(DisasContext *ctx, TCGv base, target_long ofs) return make_address_x(ctx, base, addend); } +static uint64_t make_address_pc(DisasContext *ctx, uint64_t addr) +{ + return addr; +} + #include "decode-insns.c.inc" #include "insn_trans/trans_arith.c.inc" #include "insn_trans/trans_shift.c.inc" -- cgit v1.2.3 From 7033c0e6dd36cd2bfa9a323c3a51ecb0b55903fc Mon Sep 17 00:00:00 2001 From: Jiajie Chen Date: Tue, 22 Aug 2023 09:13:55 +0200 Subject: target/loongarch: Truncate high 32 bits of address in VA32 mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When running in VA32 mode(!LA64 or VA32L[1-3] matching PLV), virtual address is truncated to 32 bits before address mapping. Signed-off-by: Jiajie Chen Co-authored-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn> Message-Id: <20230822071405.35386-10-philmd@linaro.org> --- target/loongarch/translate.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) (limited to 'target/loongarch/translate.c') diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index 8b26555a27..9a23ec786d 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -86,6 +86,10 @@ void generate_exception(DisasContext *ctx, int excp) static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) { + if (ctx->va32) { + dest = (uint32_t) dest; + } + if (translator_use_goto_tb(&ctx->base, dest)) { tcg_gen_goto_tb(n); tcg_gen_movi_tl(cpu_pc, dest); @@ -212,11 +216,17 @@ static TCGv make_address_x(DisasContext *ctx, TCGv base, TCGv addend) { TCGv temp = NULL; - if (addend) { + if (addend || ctx->va32) { temp = tcg_temp_new(); + } + if (addend) { tcg_gen_add_tl(temp, base, addend); base = temp; } + if (ctx->va32) { + tcg_gen_ext32u_tl(temp, base); + base = temp; + } return base; } @@ -262,6 +272,10 @@ static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) } ctx->base.pc_next += 4; + + if (ctx->va32) { + ctx->base.pc_next = (uint32_t)ctx->base.pc_next; + } } static void loongarch_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) -- cgit v1.2.3 From 6496269d7e0b7f0d42499d7e4dde19c8b6c759c9 Mon Sep 17 00:00:00 2001 From: Jiajie Chen Date: Tue, 22 Aug 2023 09:19:50 +0200 Subject: target/loongarch: Sign extend results in VA32 mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In VA32 mode, BL, JIRL and PC* instructions should sign-extend the low 32 bit result to 64 bits. Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230822032724.1353391-7-gaosong@loongson.cn> Message-Id: <20230822071959.35620-1-philmd@linaro.org> --- target/loongarch/translate.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'target/loongarch/translate.c') diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index 9a23ec786d..de7c1c5d1f 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -238,6 +238,9 @@ static TCGv make_address_i(DisasContext *ctx, TCGv base, target_long ofs) static uint64_t make_address_pc(DisasContext *ctx, uint64_t addr) { + if (ctx->va32) { + addr = (int32_t)addr; + } return addr; } -- cgit v1.2.3 From c0c0461e3a06c8e854b8666a2610b1b619d0d1f8 Mon Sep 17 00:00:00 2001 From: Song Gao Date: Tue, 22 Aug 2023 09:19:52 +0200 Subject: target/loongarch: Add avail_64 to check la64-only instructions The la32 instructions listed in Table 2 at https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#overview-of-basic-integer-instructions Co-authored-by: Jiajie Chen Signed-off-by: Song Gao Reviewed-by: Richard Henderson Message-ID: <20230822032724.1353391-9-gaosong@loongson.cn> Message-Id: <20230822071959.35620-3-philmd@linaro.org> --- target/loongarch/translate.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'target/loongarch/translate.c') diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index de7c1c5d1f..6967e12fc3 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -127,6 +127,8 @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase, ctx->va32 = (ctx->base.tb->flags & HW_FLAGS_VA32) != 0; ctx->zero = tcg_constant_tl(0); + + ctx->cpucfg1 = env->cpucfg[1]; } static void loongarch_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) -- cgit v1.2.3 From 95e2ca240739fc1a917102710d79a09f055f4d79 Mon Sep 17 00:00:00 2001 From: Song Gao Date: Tue, 22 Aug 2023 09:19:55 +0200 Subject: target/loongarch: Add avail_FP/FP_SP/FP_DP to check fpu instructions Signed-off-by: Song Gao Acked-by: Richard Henderson Message-ID: <20230822032724.1353391-12-gaosong@loongson.cn> Message-Id: <20230822071959.35620-6-philmd@linaro.org> --- target/loongarch/translate.c | 1 + 1 file changed, 1 insertion(+) (limited to 'target/loongarch/translate.c') diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index 6967e12fc3..fd393ed76d 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -129,6 +129,7 @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase, ctx->zero = tcg_constant_tl(0); ctx->cpucfg1 = env->cpucfg[1]; + ctx->cpucfg2 = env->cpucfg[2]; } static void loongarch_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) -- cgit v1.2.3