From 4623367697ebb531fce89a10f9c73a820a5ad82a Mon Sep 17 00:00:00 2001 From: Xiaojuan Yang Date: Fri, 1 Jul 2022 17:34:04 +0800 Subject: target/loongarch: Fix the meaning of ECFG reg's VS field By the manual of LoongArch CSR, the VS field(18:16 bits) of ECFG reg means that the number of instructions between each exception entry is 2^VS. Signed-off-by: Xiaojuan Yang Reviewed-by: Richard Henderson Message-Id: <20220701093407.2150607-9-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson --- target/loongarch/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'target/loongarch/cpu.c') diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 47c0bdd1ac..d2d4667a34 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -223,6 +223,10 @@ static void loongarch_cpu_do_interrupt(CPUState *cs) env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); + if (vec_size) { + vec_size = (1 << vec_size) * 4; + } + if (cs->exception_index == EXCCODE_INT) { /* Interrupt */ uint32_t vector = 0; -- cgit v1.2.3