From 1f5c00cfdb8114c1e3a13426588ceb64f82c9ddb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Mon, 14 Nov 2016 14:19:17 +0000 Subject: qom/cpu: move tlb_flush to cpu_common_reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It is a common thing amongst the various cpu reset functions want to flush the SoftMMU's TLB entries. This is done either by calling tlb_flush directly or by way of a general memset of the CPU structure (sometimes both). This moves the tlb_flush call to the common reset function and additionally ensures it is only done for the CONFIG_SOFTMMU case and when tcg is enabled. In some target cases we add an empty end_of_reset_fields structure to the target vCPU structure so have a clear end point for any memset which is resetting value in the structure before CPU_COMMON (where the TLB structures are). While this is a nice clean-up in general it is also a precursor for changes coming to cputlb for MTTCG where the clearing of entries can't be done arbitrarily across vCPUs. Currently the cpu_reset function is usually called from the context of another vCPU as the architectural power up sequence is run. By using the cputlb API functions we can ensure the right behaviour in the future. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Reviewed-by: David Gibson --- target/i386/cpu.c | 2 -- target/i386/cpu.h | 6 ++++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'target/i386') diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b0640f1e38..b76e1d8cb9 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2819,8 +2819,6 @@ static void x86_cpu_reset(CPUState *s) memset(env, 0, offsetof(CPUX86State, end_reset_fields)); - tlb_flush(s, 1); - env->old_exception = -1; /* init to reset state */ diff --git a/target/i386/cpu.h b/target/i386/cpu.h index a04e46b166..6c1902b36e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1123,10 +1123,12 @@ typedef struct CPUX86State { uint8_t nmi_injected; uint8_t nmi_pending; + /* Fields up to this point are cleared by a CPU reset */ + struct {} end_reset_fields; + CPU_COMMON - /* Fields from here on are preserved across CPU reset. */ - struct {} end_reset_fields; + /* Fields after CPU_COMMON are preserved across CPU reset. */ /* processor features (e.g. for CPUID insn) */ /* Minimum level/xlevel/xlevel2, based on CPU model + features */ -- cgit v1.2.3 From d10eb08f5d8389c814b554d01aa2882ac58221bf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Mon, 14 Nov 2016 14:17:28 +0000 Subject: cputlb: drop flush_global flag from tlb_flush MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We have never has the concept of global TLB entries which would avoid the flush so we never actually use this flag. Drop it and make clear that tlb_flush is the sledge-hammer it has always been. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson [DG: ppc portions] Acked-by: David Gibson --- target/i386/fpu_helper.c | 2 +- target/i386/helper.c | 8 ++++---- target/i386/machine.c | 2 +- target/i386/misc_helper.c | 2 +- target/i386/svm_helper.c | 2 +- 5 files changed, 8 insertions(+), 8 deletions(-) (limited to 'target/i386') diff --git a/target/i386/fpu_helper.c b/target/i386/fpu_helper.c index 2049a8c01d..66474ad98e 100644 --- a/target/i386/fpu_helper.c +++ b/target/i386/fpu_helper.c @@ -1465,7 +1465,7 @@ void helper_xrstor(CPUX86State *env, target_ulong ptr, uint64_t rfbm) } if (env->pkru != old_pkru) { CPUState *cs = CPU(x86_env_get_cpu(env)); - tlb_flush(cs, 1); + tlb_flush(cs); } } } diff --git a/target/i386/helper.c b/target/i386/helper.c index 43e87ddba0..c86272efab 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -586,7 +586,7 @@ void x86_cpu_set_a20(X86CPU *cpu, int a20_state) /* when a20 is changed, all the MMU mappings are invalid, so we must flush everything */ - tlb_flush(cs, 1); + tlb_flush(cs); env->a20_mask = ~(1 << 20) | (a20_state << 20); } } @@ -599,7 +599,7 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0) qemu_log_mask(CPU_LOG_MMU, "CR0 update: CR0=0x%08x\n", new_cr0); if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) != (env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) { - tlb_flush(CPU(cpu), 1); + tlb_flush(CPU(cpu)); } #ifdef TARGET_X86_64 @@ -641,7 +641,7 @@ void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3) if (env->cr[0] & CR0_PG_MASK) { qemu_log_mask(CPU_LOG_MMU, "CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3); - tlb_flush(CPU(cpu), 0); + tlb_flush(CPU(cpu)); } } @@ -656,7 +656,7 @@ void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4) if ((new_cr4 ^ env->cr[4]) & (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_LA57_MASK)) { - tlb_flush(CPU(cpu), 1); + tlb_flush(CPU(cpu)); } /* Clear bits we're going to recompute. */ diff --git a/target/i386/machine.c b/target/i386/machine.c index 760f82b6c7..e002b4fc6d 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -387,7 +387,7 @@ static int cpu_post_load(void *opaque, int version_id) env->dr[7] = dr7 & ~(DR7_GLOBAL_BP_MASK | DR7_LOCAL_BP_MASK); cpu_x86_update_dr7(env, dr7); } - tlb_flush(cs, 1); + tlb_flush(cs); if (tcg_enabled()) { cpu_smm_update(cpu); diff --git a/target/i386/misc_helper.c b/target/i386/misc_helper.c index 3f666b4b87..5029efef47 100644 --- a/target/i386/misc_helper.c +++ b/target/i386/misc_helper.c @@ -635,5 +635,5 @@ void helper_wrpkru(CPUX86State *env, uint32_t ecx, uint64_t val) } env->pkru = val; - tlb_flush(cs, 1); + tlb_flush(cs); } diff --git a/target/i386/svm_helper.c b/target/i386/svm_helper.c index 782b3f12f0..210f6aa7b5 100644 --- a/target/i386/svm_helper.c +++ b/target/i386/svm_helper.c @@ -289,7 +289,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) break; case TLB_CONTROL_FLUSH_ALL_ASID: /* FIXME: this is not 100% correct but should work for now */ - tlb_flush(cs, 1); + tlb_flush(cs); break; } -- cgit v1.2.3