From a764f3f7197f4d7ad8fe8424269933de912224cb Mon Sep 17 00:00:00 2001 From: Konrad Rzeszutek Wilk Date: Fri, 1 Jun 2018 11:38:08 -0400 Subject: i386: define the AMD 'amd-ssbd' CPUID feature bit AMD future CPUs expose _two_ ways to utilize the Intel equivalant of the Speculative Store Bypass Disable. The first is via the virtualized VIRT_SPEC CTRL MSR (0xC001_011f) and the second is via the SPEC_CTRL MSR (0x48). The document titled: 124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf gives priority of SPEC CTRL MSR over the VIRT SPEC CTRL MSR. A copy of this document is available at https://bugzilla.kernel.org/show_bug.cgi?id=199889 Anyhow, this means that on future AMD CPUs there will be _two_ ways to deal with SSBD. Signed-off-by: Konrad Rzeszutek Wilk Message-Id: <20180601153809.15259-2-konrad.wilk@oracle.com> Signed-off-by: Eduardo Habkost --- target/i386/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target/i386/cpu.c') diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d7dfefcde0..7234bebfcb 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1009,7 +1009,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { "ibpb", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, "virt-ssbd", NULL, NULL, + "amd-ssbd", "virt-ssbd", NULL, NULL, NULL, NULL, NULL, NULL, }, .cpuid_eax = 0x80000008, -- cgit v1.2.3