From 5718cef05a0fe306646dd0481eb6ccf4fef3979e Mon Sep 17 00:00:00 2001 From: Michael Rolnik Date: Fri, 24 Jan 2020 01:51:13 +0100 Subject: target/avr: Add instruction translation - Bit and Bit-test Instructions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This includes: - LSR, ROR - ASR - SWAP - SBI, CBI - BST, BLD - BSET, BCLR Signed-off-by: Michael Rolnik Signed-off-by: Richard Henderson Signed-off-by: Aleksandar Markovic Tested-by: Philippe Mathieu-Daudé Reviewed-by: Aleksandar Markovic Signed-off-by: Thomas Huth Message-Id: <20200705140315.260514-15-huth@tuxfamily.org> Signed-off-by: Philippe Mathieu-Daudé --- target/avr/insn.decode | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'target/avr/insn.decode') diff --git a/target/avr/insn.decode b/target/avr/insn.decode index 279ddfbc0c..7bb6ce7495 100644 --- a/target/avr/insn.decode +++ b/target/avr/insn.decode @@ -163,3 +163,17 @@ XCH 1001 001 rd:5 0100 LAC 1001 001 rd:5 0110 LAS 1001 001 rd:5 0101 LAT 1001 001 rd:5 0111 + +# +# Bit and Bit-test Instructions +# +LSR 1001 010 rd:5 0110 +ROR 1001 010 rd:5 0111 +ASR 1001 010 rd:5 0101 +SWAP 1001 010 rd:5 0010 +SBI 1001 1010 reg:5 bit:3 +CBI 1001 1000 reg:5 bit:3 +BST 1111 101 rd:5 0 bit:3 +BLD 1111 100 rd:5 0 bit:3 +BSET 1001 0100 0 bit:3 1000 +BCLR 1001 0100 1 bit:3 1000 -- cgit v1.2.3