From b26b5629c0be4a9539833de4189184a224590d14 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 20 May 2021 16:28:38 +0100 Subject: target/arm: Make FPSCR.LTPSIZE writable for MVE The M-profile FPSCR has an LTPSIZE field, but if MVE is not implemented it is read-only and always reads as 4; this is how QEMU currently handles it. Make the field writable when MVE is implemented. We can safely add the field to the MVE migration struct because currently no CPUs enable MVE and so the migration struct is never used. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210520152840.24453-8-peter.maydell@linaro.org --- target/arm/vfp_helper.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'target/arm/vfp_helper.c') diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 01b9d8557f..e0886ab5a5 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -195,8 +195,10 @@ uint32_t vfp_get_fpscr(CPUARMState *env) void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) { + ARMCPU *cpu = env_archcpu(env); + /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ - if (!cpu_isar_feature(any_fp16, env_archcpu(env))) { + if (!cpu_isar_feature(any_fp16, cpu)) { val &= ~FPCR_FZ16; } @@ -210,11 +212,12 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) * because in v7A no-short-vector-support cores still had to * allow Stride/Len to be written with the only effect that * some insns are required to UNDEF if the guest sets them. - * - * TODO: if M-profile MVE implemented, set LTPSIZE. */ env->vfp.vec_len = extract32(val, 16, 3); env->vfp.vec_stride = extract32(val, 20, 2); + } else if (cpu_isar_feature(aa32_mve, cpu)) { + env->v7m.ltpsize = extract32(val, FPCR_LTPSIZE_SHIFT, + FPCR_LTPSIZE_LENGTH); } if (arm_feature(env, ARM_FEATURE_NEON)) { -- cgit v1.2.3