From aaae563bc73de0598bbc09a102e68f27fafe704a Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 6 Aug 2020 11:44:52 +0100 Subject: target/arm: Implement FPST_STD_F16 fpstatus MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Architecturally, Neon FP16 operations use the "standard FPSCR" like all other Neon operations. However, this is defined in the Arm ARM pseudocode as "a fixed value, except that FZ16 (and AHP) follow the FPSCR bits". In QEMU, the softfloat float_status doesn't include separate flush-to-zero for FP16 operations, so we must keep separate fp_status for "Neon non-FP16" and "Neon fp16" operations, in the same way we do already for the non-Neon "fp_status" vs "fp_status_f16". Add the extra float_status field to the CPU state structure, ensure it is correctly initialized and updated on FPSCR writes, and make fpstatus_ptr(FPST_STD_F16) return a pointer to it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée Message-id: 20200806104453.30393-4-peter.maydell@linaro.org --- target/arm/translate.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'target/arm/translate.h') diff --git a/target/arm/translate.h b/target/arm/translate.h index e3680e6547..6d6d4c0f42 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -436,7 +436,8 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour) offset = offsetof(CPUARMState, vfp.standard_fp_status); break; case FPST_STD_F16: - /* Not yet used or implemented: fall through to assert */ + offset = offsetof(CPUARMState, vfp.standard_fp_status_f16); + break; default: g_assert_not_reached(); } -- cgit v1.2.3