From fb661dac05826a2a6c77368c84f4e1870bd9cec7 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 16 Aug 2018 14:05:29 +0100 Subject: target/arm: Use FZ not FZ16 for SVE FCVT single-half and double-half We were using the wrong flush-to-zero bit for the non-half input. Fixes: 46d33d1e3c9 Cc: qemu-stable@nongnu.org (3.0.1) Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson Reviewed-by: Laurent Desnogues Tested-by: Laurent Desnogues Message-id: 20180810193129.1556-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell (cherry picked from commit e4ab5124a5c2e2291006b24bdc21c3dd8d087ff4) Signed-off-by: Michael Roth --- target/arm/translate-sve.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'target/arm/translate-sve.c') diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index d27bc8c946..667879564f 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4093,7 +4093,7 @@ static bool do_zpz_ptr(DisasContext *s, int rd, int rn, int pg, static bool trans_FCVT_sh(DisasContext *s, arg_rpr_esz *a, uint32_t insn) { - return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvt_sh); + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_sh); } static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a, uint32_t insn) @@ -4103,7 +4103,7 @@ static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a, uint32_t insn) static bool trans_FCVT_dh(DisasContext *s, arg_rpr_esz *a, uint32_t insn) { - return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvt_dh); + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_dh); } static bool trans_FCVT_hd(DisasContext *s, arg_rpr_esz *a, uint32_t insn) -- cgit v1.2.3