From 83ff3d6add965c9752324de11eac5687121ea826 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 19 Nov 2020 21:55:53 +0000 Subject: target/arm: Implement VSCCLRM insn Implement the v8.1M VSCCLRM insn, which zeros floating point registers if there is an active floating point context. This requires support in write_neon_element32() for the MO_32 element size, so add it. Because we want to use arm_gen_condlabel(), we need to move the definition of that function up in translate.c so it is before the #include of translate-vfp.c.inc. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201119215617.29887-5-peter.maydell@linaro.org --- target/arm/m-nocp.decode | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'target/arm/m-nocp.decode') diff --git a/target/arm/m-nocp.decode b/target/arm/m-nocp.decode index 28c8ac6b94..ccd62e8739 100644 --- a/target/arm/m-nocp.decode +++ b/target/arm/m-nocp.decode @@ -29,13 +29,17 @@ # If the coprocessor is not present or disabled then we will generate # the NOCP exception; otherwise we let the insn through to the main decode. +%vd_dp 22:1 12:4 +%vd_sp 12:4 22:1 + &nocp cp { # Special cases which do not take an early NOCP: VLLDM and VLSTM VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000 - # TODO: VSCCLRM (new in v8.1M) is similar: - #VSCCLRM 1110 1100 1-01 1111 ---- 1011 ---- ---0 + # VSCCLRM (new in v8.1M) is similar: + VSCCLRM 1110 1100 1.01 1111 .... 1011 imm:7 0 vd=%vd_dp size=3 + VSCCLRM 1110 1100 1.01 1111 .... 1010 imm:8 vd=%vd_sp size=2 NOCP 111- 1110 ---- ---- ---- cp:4 ---- ---- &nocp NOCP 111- 110- ---- ---- ---- cp:4 ---- ---- &nocp -- cgit v1.2.3