From ff730e9666a716b669ac4a8ca7c521177d1d2b15 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 1 Mar 2019 12:04:55 -0800 Subject: target/arm: Split helper_msr_i_pstate into 3 The EL0+UMA check is unique to DAIF. While SPSel had avoided the check by nature of already checking EL >= 1, the other post v8.0 extensions to MSR (imm) allow EL0 and do not require UMA. Avoid the unconditional write to pc and use raise_exception_ra to unwind. Signed-off-by: Richard Henderson Message-id: 20190301200501.16533-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/internals.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'target/arm/internals.h') diff --git a/target/arm/internals.h b/target/arm/internals.h index a4bd1becb7..587a1ddf58 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -968,4 +968,19 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data); +static inline int exception_target_el(CPUARMState *env) +{ + int target_el = MAX(1, arm_current_el(env)); + + /* + * No such thing as secure EL1 if EL3 is aarch32, + * so update the target EL to EL3 in this case. + */ + if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) { + target_el = 3; + } + + return target_el; +} + #endif -- cgit v1.2.3