From 2bd5f41c00686a1f847a60824d0375f3df2c26bf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Thu, 15 Aug 2019 09:46:41 +0100 Subject: target/arm: generate a custom MIDR for -cpu max MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit While most features are now detected by probing the ID_* registers kernels can (and do) use MIDR_EL1 for working out of they have to apply errata. This can trip up warnings in the kernel as it tries to work out if it should apply workarounds to features that don't actually exist in the reported CPU type. Avoid this problem by synthesising our own MIDR value. Signed-off-by: Alex Bennée Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20190726113950.7499-1-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu64.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'target/arm/cpu64.c') diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1901997a06..ee55237a9b 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -296,6 +296,25 @@ static void aarch64_max_initfn(Object *obj) uint32_t u; aarch64_a57_initfn(obj); + /* + * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real + * one and try to apply errata workarounds or use impdef features we + * don't provide. + * An IMPLEMENTER field of 0 means "reserved for software use"; + * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers + * to see which features are present"; + * the VARIANT, PARTNUM and REVISION fields are all implementation + * defined and we choose to define PARTNUM just in case guest + * code needs to distinguish this QEMU CPU from other software + * implementations, though this shouldn't be needed. + */ + t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0); + t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); + t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q'); + t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0); + t = FIELD_DP64(t, MIDR_EL1, REVISION, 0); + cpu->midr = t; + t = cpu->isar.id_aa64isar0; t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); -- cgit v1.2.3 From b9e758f0b5bc64b5800432c0a436dd1afc98ba33 Mon Sep 17 00:00:00 2001 From: Andrew Jones Date: Fri, 2 Aug 2019 14:25:26 +0200 Subject: target/arm/cpu64: Ensure kvm really supports aarch64=off If -cpu ,aarch64=off is used then KVM must also be used, and it and the host must support running the vcpu in 32-bit mode. Also, if -cpu ,aarch64=on is used, then it doesn't matter if kvm is enabled or not. Signed-off-by: Andrew Jones Reviewed-by: Eric Auger Signed-off-by: Peter Maydell --- target/arm/cpu64.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'target/arm/cpu64.c') diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index ee55237a9b..ab63115c77 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -426,13 +426,13 @@ static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp) * restriction allows us to avoid fixing up functionality that assumes a * uniform execution state like do_interrupt. */ - if (!kvm_enabled()) { - error_setg(errp, "'aarch64' feature cannot be disabled " - "unless KVM is enabled"); - return; - } - if (value == false) { + if (!kvm_enabled() || !kvm_arm_aarch32_supported(CPU(cpu))) { + error_setg(errp, "'aarch64' feature cannot be disabled " + "unless KVM is enabled and 32-bit EL1 " + "is supported"); + return; + } unset_feature(&cpu->env, ARM_FEATURE_AARCH64); } else { set_feature(&cpu->env, ARM_FEATURE_AARCH64); -- cgit v1.2.3