From 56ec06bb8ea5467f09b0f351e98816a2876111e7 Mon Sep 17 00:00:00 2001 From: blueswir1 Date: Sun, 9 Mar 2008 20:46:51 +0000 Subject: Convert andn, orn and xnor to TCG git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4030 c046a42c-6fe2-441c-8c8c-71466251a162 --- target-sparc/op.c | 15 --------------- target-sparc/translate.c | 9 ++++++--- 2 files changed, 6 insertions(+), 18 deletions(-) (limited to 'target-sparc') diff --git a/target-sparc/op.c b/target-sparc/op.c index 7042047107..e57a60d357 100644 --- a/target-sparc/op.c +++ b/target-sparc/op.c @@ -554,21 +554,6 @@ void OPPROTO op_tsub_T1_T0_ccTV(void) FORCE_RET(); } -void OPPROTO op_andn_T1_T0(void) -{ - T0 &= ~T1; -} - -void OPPROTO op_orn_T1_T0(void) -{ - T0 |= ~T1; -} - -void OPPROTO op_xnor_T1_T0(void) -{ - T0 ^= ~T1; -} - void OPPROTO op_umul_T1_T0(void) { uint64_t res; diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 81b1c41ae5..42ddfc4f27 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -2613,17 +2613,20 @@ static void disas_sparc_insn(DisasContext * dc) tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); break; case 0x5: - gen_op_andn_T1_T0(); + tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1); + tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]); if (xop & 0x10) gen_op_logic_T0_cc(); break; case 0x6: - gen_op_orn_T1_T0(); + tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1); + tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); if (xop & 0x10) gen_op_logic_T0_cc(); break; case 0x7: - gen_op_xnor_T1_T0(); + tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1); + tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]); if (xop & 0x10) gen_op_logic_T0_cc(); break; -- cgit v1.2.3