From e8af50a30e89e5cfdc1b2a2fa8fab3ce463a4790 Mon Sep 17 00:00:00 2001
From: bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Thu, 30 Sep 2004 21:55:55 +0000
Subject: full system SPARC emulation (Blue Swirl)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1083 c046a42c-6fe2-441c-8c8c-71466251a162
---
 target-sparc/fop_template.h | 121 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 121 insertions(+)
 create mode 100644 target-sparc/fop_template.h

(limited to 'target-sparc/fop_template.h')

diff --git a/target-sparc/fop_template.h b/target-sparc/fop_template.h
new file mode 100644
index 0000000000..2987b68d64
--- /dev/null
+++ b/target-sparc/fop_template.h
@@ -0,0 +1,121 @@
+/*
+ *  SPARC micro operations (templates for various register related
+ *  operations)
+ * 
+ *  Copyright (c) 2003 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+/* floating point registers moves */
+void OPPROTO glue(op_load_fpr_FT0_fpr, REGNAME)(void)
+{
+    FT0 = REG;
+}
+
+void OPPROTO glue(op_store_FT0_fpr_fpr, REGNAME)(void)
+{
+    REG = FT0;
+}
+
+void OPPROTO glue(op_load_fpr_FT1_fpr, REGNAME)(void)
+{
+    FT1 = REG;
+}
+
+void OPPROTO glue(op_store_FT1_fpr_fpr, REGNAME)(void)
+{
+    REG = FT1;
+}
+
+void OPPROTO glue(op_load_fpr_FT2_fpr, REGNAME)(void)
+{
+    FT2 = REG;
+}
+
+void OPPROTO glue(op_store_FT2_fpr_fpr, REGNAME)(void)
+{
+    REG = FT2;
+}
+
+/* double floating point registers moves */
+#if 0
+#define CPU_DOUBLE_U_DEF
+typedef union {
+    double d;
+    struct {
+        uint32_t lower;
+        uint32_t upper;
+    } l;
+    uint64_t ll;
+} CPU_DoubleU;
+#endif /* CPU_DOUBLE_U_DEF */
+
+void OPPROTO glue(op_load_fpr_DT0_fpr, REGNAME)(void)
+{
+    CPU_DoubleU u;
+    uint32_t *p = (uint32_t *)&REG;
+    u.l.lower = *(p +1);
+    u.l.upper = *p;
+    DT0 = u.d;
+}
+
+void OPPROTO glue(op_store_DT0_fpr_fpr, REGNAME)(void)
+{
+    CPU_DoubleU u;
+    uint32_t *p = (uint32_t *)&REG;
+    u.d = DT0;
+    *(p +1) = u.l.lower;
+    *p = u.l.upper;
+}
+
+void OPPROTO glue(op_load_fpr_DT1_fpr, REGNAME)(void)
+{
+    CPU_DoubleU u;
+    uint32_t *p = (uint32_t *)&REG;
+    u.l.lower = *(p +1);
+    u.l.upper = *p;
+    DT1 = u.d;
+}
+
+void OPPROTO glue(op_store_DT1_fpr_fpr, REGNAME)(void)
+{
+    CPU_DoubleU u;
+    uint32_t *p = (uint32_t *)&REG;
+    u.d = DT1;
+    *(p +1) = u.l.lower;
+    *p = u.l.upper;
+}
+
+void OPPROTO glue(op_load_fpr_DT2_fpr, REGNAME)(void)
+{
+    CPU_DoubleU u;
+    uint32_t *p = (uint32_t *)&REG;
+    u.l.lower = *(p +1);
+    u.l.upper = *p;
+    DT2 = u.d;
+}
+
+void OPPROTO glue(op_store_DT2_fpr_fpr, REGNAME)(void)
+{
+    CPU_DoubleU u;
+    uint32_t *p = (uint32_t *)&REG;
+    u.d = DT2;
+    *(p +1) = u.l.lower;
+    *p = u.l.upper;
+}
+
+#undef REG
+#undef REGNAME
-- 
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