From 4d2c2b77f3d0c59642dd2ce799a0fb4c2a91aca8 Mon Sep 17 00:00:00 2001 From: Blue Swirl Date: Sat, 18 Jun 2011 20:27:05 +0000 Subject: Sparc32: dummy implementation of MXCC MMU breakpoint registers Add dummy registers for SuperSPARC MXCC MMU counter breakpoints, save and load all MXCC registers. Signed-off-by: Blue Swirl --- target-sparc/cpu.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'target-sparc/cpu.h') diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 320530ec9f..a220bf497d 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -403,6 +403,8 @@ typedef struct CPUSPARCState { uint32_t mmuregs[32]; uint64_t mxccdata[4]; uint64_t mxccregs[8]; + uint32_t mmubpctrv, mmubpctrc, mmubpctrs; + uint64_t mmubpaction; uint64_t mmubpregs[4]; uint64_t prom_addr; #endif @@ -521,7 +523,7 @@ int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); #define cpu_signal_handler cpu_sparc_signal_handler #define cpu_list sparc_cpu_list -#define CPU_SAVE_VERSION 6 +#define CPU_SAVE_VERSION 7 /* MMU modes definitions */ #if defined (TARGET_SPARC64) -- cgit v1.2.3