From 706d64675ac2cd72d803cb2f28aa3a332c402ba9 Mon Sep 17 00:00:00 2001 From: "Aneesh Kumar K.V" Date: Tue, 26 Jul 2016 17:28:24 +0530 Subject: target-ppc: Introduce Power9 family The patch adds CPU PVR definition for POWER9 and enables QEMU to launch guests/linux-user in TCG mode. Signed-off-by: Aneesh Kumar K.V [ Added POWER9 alias, POWER9 SPAPR core and dropped MMU defines ] Signed-off-by: Nikunj A Dadhania [dwg: Dropped sPAPR core type again for now] Signed-off-by: David Gibson --- target-ppc/translate_init.c | 86 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 85 insertions(+), 1 deletion(-) (limited to 'target-ppc/translate_init.c') diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 7a9b15e7e1..2d29ad82cd 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7459,7 +7459,8 @@ enum BOOK3S_CPU_TYPE { BOOK3S_CPU_POWER5PLUS, BOOK3S_CPU_POWER6, BOOK3S_CPU_POWER7, - BOOK3S_CPU_POWER8 + BOOK3S_CPU_POWER8, + BOOK3S_CPU_POWER9 }; static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, @@ -8241,6 +8242,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version) break; case BOOK3S_CPU_POWER7: case BOOK3S_CPU_POWER8: + case BOOK3S_CPU_POWER9: gen_spr_book3s_ids(env); gen_spr_amr(env, version >= BOOK3S_CPU_POWER8); gen_spr_book3s_purr(env); @@ -8293,6 +8295,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version) break; case BOOK3S_CPU_POWER7: case BOOK3S_CPU_POWER8: + case BOOK3S_CPU_POWER9: default: env->slb_nr = 32; break; @@ -8310,6 +8313,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version) ppcPOWER7_irq_init(ppc_env_get_cpu(env)); break; case BOOK3S_CPU_POWER8: + case BOOK3S_CPU_POWER9: init_excp_POWER8(env); ppcPOWER7_irq_init(ppc_env_get_cpu(env)); break; @@ -8772,6 +8776,86 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) pcc->l1_icache_size = 0x8000; pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; } +static void init_proc_POWER9(CPUPPCState *env) +{ + init_proc_book3s_64(env, BOOK3S_CPU_POWER9); +} + +static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) +{ + if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) { + return true; + } + return false; +} + +POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); + + dc->fw_name = "PowerPC,POWER9"; + dc->desc = "POWER9"; + dc->props = powerpc_servercpu_properties; + pcc->pvr_match = ppc_pvr_match_power9; + pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; + pcc->init_proc = init_proc_POWER9; + pcc->check_pow = check_pow_nocheck; + pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | + PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | + PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | + PPC_FLOAT_FRSQRTES | + PPC_FLOAT_STFIWX | + PPC_FLOAT_EXT | + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | + PPC_MEM_SYNC | PPC_MEM_EIEIO | + PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | + PPC_64B | PPC_64BX | PPC_ALTIVEC | + PPC_SEGMENT_64B | PPC_SLBI | + PPC_POPCNTB | PPC_POPCNTWD | + PPC_CILDST; + pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | + PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | + PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | + PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | + PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | + PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | + PPC2_TM | PPC2_PM_ISA206; + pcc->msr_mask = (1ull << MSR_SF) | + (1ull << MSR_TM) | + (1ull << MSR_VR) | + (1ull << MSR_VSX) | + (1ull << MSR_EE) | + (1ull << MSR_PR) | + (1ull << MSR_FP) | + (1ull << MSR_ME) | + (1ull << MSR_FE0) | + (1ull << MSR_SE) | + (1ull << MSR_DE) | + (1ull << MSR_FE1) | + (1ull << MSR_IR) | + (1ull << MSR_DR) | + (1ull << MSR_PMM) | + (1ull << MSR_RI) | + (1ull << MSR_LE); + /* Using 2.07 defines until new radix model is added. */ + pcc->mmu_model = POWERPC_MMU_2_07; +#if defined(CONFIG_SOFTMMU) + pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; + /* segment page size remain the same */ + pcc->sps = &POWER7_POWER8_sps; +#endif + pcc->excp_model = POWERPC_EXCP_POWER8; + pcc->bus_model = PPC_FLAGS_INPUT_POWER7; + pcc->bfd_mach = bfd_mach_ppc64; + pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | + POWERPC_FLAG_BE | POWERPC_FLAG_PMM | + POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | + POWERPC_FLAG_VSX | POWERPC_FLAG_TM; + pcc->l1_dcache_size = 0x8000; + pcc->l1_icache_size = 0x8000; + pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; +} #if !defined(CONFIG_USER_ONLY) -- cgit v1.2.3