From 1f29871cb7518692cf5c1fa8c19b117c789ff7f0 Mon Sep 17 00:00:00 2001 From: Tom Musta Date: Tue, 22 Oct 2013 22:06:17 +1100 Subject: Add MSR VSX and Associated Exception This patch adds support for the VSX bit of the PowerPC Machine State Register (MSR) as well as the corresponding VSX Unavailable exception. The VSX bit is added to the defined bits masks of the Power7 and Power8 CPU models. Signed-off-by: Tom Musta Signed-off-by: Anton Blanchard Signed-off-by: Alexander Graf --- target-ppc/translate.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'target-ppc/translate.c') diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 66c777174c..415f5d14e1 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -195,6 +195,7 @@ typedef struct DisasContext { #endif int fpu_enabled; int altivec_enabled; + int vsx_enabled; int spe_enabled; ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ int singlestep_enabled; @@ -9759,6 +9760,11 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu, ctx.altivec_enabled = msr_vr; else ctx.altivec_enabled = 0; + if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { + ctx.vsx_enabled = msr_vsx; + } else { + ctx.vsx_enabled = 0; + } if ((env->flags & POWERPC_FLAG_SE) && msr_se) ctx.singlestep_enabled = CPU_SINGLE_STEP; else -- cgit v1.2.3