From a721d390b302a383a99224e08d12caad2e97d7ab Mon Sep 17 00:00:00 2001 From: Alex Zuepke Date: Wed, 28 May 2014 19:25:36 +0200 Subject: PPC: e500: Fix MMUCSR0 emulation A "mtspr SPRMMUCSR0, reg" always flushed TLB0, because it passed the SPR number 0x3f4 to the flush routine. But we want to flush either TLB0 or TBL1 depending on the GPR value. Signed-off-by: Alex Zuepke [agraf: change subject line, fix TCGv size mismatch] Signed-off-by: Alexander Graf --- target-ppc/mmu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'target-ppc/mmu_helper.c') diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index f029f41965..1e70536e36 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -2886,7 +2886,7 @@ void helper_booke206_tlbilx3(CPUPPCState *env, target_ulong address) tlb_flush(CPU(cpu), 1); } -void helper_booke206_tlbflush(CPUPPCState *env, uint32_t type) +void helper_booke206_tlbflush(CPUPPCState *env, target_ulong type) { int flags = 0; -- cgit v1.2.3