From 9fb044911444fdd09f5f072ad0ca269d7f8b841d Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Tue, 3 May 2016 18:03:24 +0200 Subject: ppc: Use split I/D mmu modes to avoid flushes on interrupts We rework the way the MMU indices are calculated, providing separate indices for I and D side based on MSR:IR and MSR:DR respectively, and thus no longer need to flush the TLB on context changes. This also adds correct support for HV as a separate address space. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: David Gibson --- target-ppc/machine.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'target-ppc/machine.c') diff --git a/target-ppc/machine.c b/target-ppc/machine.c index f6c7256974..4820f22377 100644 --- a/target-ppc/machine.c +++ b/target-ppc/machine.c @@ -97,9 +97,12 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int version_id) qemu_get_betls(f, &env->nip); qemu_get_betls(f, &env->hflags); qemu_get_betls(f, &env->hflags_nmsr); - qemu_get_sbe32s(f, &env->mmu_idx); + qemu_get_sbe32(f); /* Discard unused mmu_idx */ qemu_get_sbe32(f); /* Discard unused power_mode */ + /* Recompute mmu indices */ + hreg_compute_mem_idx(env); + return 0; } -- cgit v1.2.3