From a9d9eb8fd45279fa8455afa03331296dbe2871ff Mon Sep 17 00:00:00 2001
From: j_mayer <j_mayer@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Sun, 7 Oct 2007 18:19:26 +0000
Subject: Implement PowerPC Altivec load & stores, used by Apple firmware for
 memcpy.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3349 c046a42c-6fe2-441c-8c8c-71466251a162
---
 target-ppc/cpu.h | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

(limited to 'target-ppc/cpu.h')

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index ef70fa0347..9cbd1c9aa5 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -292,7 +292,7 @@ typedef struct CPUPPCState CPUPPCState;
 typedef struct ppc_tb_t ppc_tb_t;
 typedef struct ppc_spr_t ppc_spr_t;
 typedef struct ppc_dcr_t ppc_dcr_t;
-typedef struct ppc_avr_t ppc_avr_t;
+typedef union ppc_avr_t ppc_avr_t;
 typedef union ppc_tlb_t ppc_tlb_t;
 
 /* SPR access micro-ops generations callbacks */
@@ -311,8 +311,11 @@ struct ppc_spr_t {
 };
 
 /* Altivec registers (128 bits) */
-struct ppc_avr_t {
-    uint32_t u[4];
+union ppc_avr_t {
+    uint8_t u8[16];
+    uint16_t u16[8];
+    uint32_t u32[4];
+    uint64_t u64[2];
 };
 
 /* Software TLB cache */
@@ -454,7 +457,7 @@ struct CPUPPCState {
      */
     ppc_gpr_t t0, t1, t2;
 #endif
-    ppc_avr_t t0_avr, t1_avr, t2_avr;
+    ppc_avr_t avr0, avr1, avr2;
 
     /* general purpose registers */
     ppc_gpr_t gpr[32];
-- 
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