From 8dfa3a5e85eca94a93b1495136f49c5776fd5ada Mon Sep 17 00:00:00 2001 From: Alexey Kardashevskiy Date: Fri, 23 May 2014 12:26:50 +1000 Subject: target-ppc: Add "compat" CPU option PowerISA defines a compatibility mode for server POWERPC CPUs which is supported by the PCR special register which is hypervisor privileged. To support this mode for guests, SPAPR defines a set of virtual PVRs, one per PowerISA spec version. When a hypervisor needs a guest to work in a compatibility mode, it puts a virtual PVR value into @cpu-version property of a CPU node. This introduces a "compat" CPU option which defines maximal compatibility mode enabled. The supported modes are power6/power7/power8. This does not change the existing behaviour, new property will be used by next patches. Signed-off-by: Alexey Kardashevskiy Signed-off-by: Alexander Graf --- target-ppc/cpu-models.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'target-ppc/cpu-models.h') diff --git a/target-ppc/cpu-models.h b/target-ppc/cpu-models.h index 9a003b43b4..db75896012 100644 --- a/target-ppc/cpu-models.h +++ b/target-ppc/cpu-models.h @@ -595,6 +595,16 @@ enum { CPU_POWERPC_PA6T = 0x00900000, }; +/* Logical PVR definitions for sPAPR */ +enum { + CPU_POWERPC_LOGICAL_2_04 = 0x0F000001, + CPU_POWERPC_LOGICAL_2_05 = 0x0F000002, + CPU_POWERPC_LOGICAL_2_06 = 0x0F000003, + CPU_POWERPC_LOGICAL_2_06_PLUS = 0x0F100003, + CPU_POWERPC_LOGICAL_2_07 = 0x0F000004, + CPU_POWERPC_LOGICAL_2_08 = 0x0F000005, +}; + /* System version register (used on MPC 8xxx) */ enum { POWERPC_SVR_NONE = 0x00000000, -- cgit v1.2.3